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8-bit flash mcu with op amps & comparators HT45F12 revision: v1.00 date: ? e ? te ?? e ? ??? ? 01 ? ? e ? te ?? e ? ??? ? 01 ?
rev. 0.00 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 3 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators table of contents eates cpu featu ? es ......................................................................................................................... ? pe ? i ? he ? al featu ? es ................................................................................................................. ? gene?al desc?i?tion ........................................................................................ 7 block diag?a? .................................................................................................. 7 pin assign?ent ........... ..................................................................................... 8 pin desc?i?tion .......... ...................................................................................... 9 a?solute maxi?u? ratings .......................................................................... 10 d.c. cha?acte?istics ........................................................................................ 11 a.c. cha?acte?istics ....................................................................................... 13 op amplifer electrical characteristics comparator electrical characteristics ldo 2.4v electrical characteristics ldo 3.3v electrical characteristics clocking and pi ? elining ......................................................................................................... 1 ? p ? og ? a ? counte ? C pc ............. ............................................................................................. 17 ? tack ..................................................................................................................................... 18 a ? ith ? etic and logic unit C alu ........................................................................................... 18 flash p?og?a? me?o?y ................................................................................. 19 ? t ? uctu ? e ................................................................................................................................ 19 ?? ecial vecto ? s ..................................................................................................................... 19 look-u ? ta ? le ............. ........................................................................................................... ? 0 ta ? le p ? og ? a ? exa ?? le ........................................................................................................ ? 1 in ci ? cuit p ? og ? a ?? ing ......................................................................................................... ?? ram data me?o?y ......................................................................................... ?3 ? t ? uctu ? e ................................................................................................................................ ? 4 ??ecial function registe? desc?i?tion ........................................................ ?5 indi ? ect add ? essing registe ? s C iar0 ? iar1 ......................................................................... ? 5 me ? o ? y pointe ? s C mp0 ? mp1 .............................................................................................. ? 5 bank pointe ? C bp ................................................................................................................. ?? accu ? ulato ? C acc ............................................................................................................... ?? p ? og ? a ? counte ? low registe ? C pcl .................................................................................. ?? look-u ? ta ? le registe ? s C tblp ? tbhp ? tblh ..................................................................... ?? ? tatus registe ? C ? tatu ? .................................................................................................... ? 7 ? yste ? cont ? ol registe ? C ctrl .......................................................................................... ? 8
rev. 0.00 ? ?e?te??e? ??? ?01? rev. 0.00 3 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators eeprom data memory ........... ....................................................................... 29 eeprom data me ? o ? y ? t ? uctu ? e ........................................................................................ ? 9 eeprom registe ? s ............ .................................................................................................. ? 9 reading data f ? o ? the eeprom ......................................................................................... 31 w ? iting data to the eeprom ................................................................................................ 31 w ? ite p ? otection ..................................................................................................................... 31 eeprom inte ?? u ? t ............. ................................................................................................... 31 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 3 ? oscillator ....................................................................................................... 33 oscillato ? ove ? view ............. .................................................................................................. 33 system clock confgurations ................................................................................................ 33 exte ? nal c ? ystal/ce ? a ? ic oscillato ? C hxt ........................................................................... 34 exte ? nal rc oscillato ? C erc ............. .................................................................................. 35 exte ? nal oscillato ? C ec ........................................................................................................ 35 inte ? nal rc oscillato ? C hirc ............. .................................................................................. 35 inte ? nal 3 ? khz oscillato ? C lirc ........................................................................................... 35 operating modes and system clocks ........................................................ 36 ? yste ? clocks ...................................................................................................................... 3 ? ? yste ? o ? e ? ation modes ...................................................................................................... 3 ? cont ? ol registe ? .................................................................................................................... 39 fast wake-u ? ........................................................................................................................ 40 o ? e ? ating mode ? witching and wake-u ? .............................................................................. 41 ? low mode to normal mode ? witching ........................................................................... 43 ente ? ing the ? leep0 mod e .................................................................................................. 43 ente ? ing the ? leep 1 mode .................................................................................................. 43 ente ? ing the idle0 mode ...................................................................................................... 43 ente ? ing the idle1 mode ...................................................................................................... 44 ? tand ? y cu ?? ent conside ? ations ........................................................................................... 44 wake-u ? ................................................................................................................................ 44 watchdog timer ........... .................................................................................. 45 watchdog ti ? e ? clock ? ou ? ce .............................................................................................. 45 watchdog ti ? e ? cont ? ol registe ? ............. ............................................................................ 45 watchdog ti ? e ? o ? e ? ation ................................................................................................... 4 ? reset and initialisation .................................................................................. 48 reset functions ............. ....................................................................................................... 48 reset initial conditions ......................................................................................................... 50 input/output ports ......................................................................................... 52 pull-high resisto ? s ................................................................................................................ 5 ? po ? t a wake-u ? ............. ........................................................................................................ 53 i/o po ? t cont ? ol registe ? s ..................................................................................................... 54 i/o pin ? t ? uctu ? es .................................................................................................................. 55 p ? og ? a ?? ing conside ? ations ............. ................................................................................... 5 ?
rev. 0.00 4 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 5 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators timer/event counter ..................................................................................... 56 ti ? e ? cont ? ol registe ? C tmrc ............................................................................................ 57 confguring the timer mode .................................................................................................. 58 confguring the event counter mode .................................................................................... 58 pulse width ca ? tu ? e mode ................................................................................................... 59 p ? og ? a ?? a ? le f ? equency divide ? C pfd ............. ................................................................ ? 0 p ? escale ? ............................................................................................................................... ? 1 i/o inte ? facing ........................................................................................................................ ? 1 ti ? e ? /event counte ? pin inte ? nal filte ? ................................................................................. ? 1 p ? og ? a ?? ing conside ? ations ............. ................................................................................... ? 1 ti ? e ? p ? og ? a ? exa ?? le ....................................................................................................... ?? ldo function .................................................................................................. 63 operational amplifers .......... ........................................................................ 64 operational amplifer registers ............. ................................................................................ ? 4 operational amplifer operation ............. ............................................................................... ? 7 operational amplifer functions ............. ............................................................................... ? 7 comparator .......... .......................................................................................... 71 co ?? a ? ato ? o ? e ? ation .......................................................................................................... 71 co ?? a ? ato ? registe ? s ........................................................................................................... 71 co ?? a ? ato ? functions ............. .............................................................................................. 73 interrupts ........................................................................................................ 75 inte ?? u ? t registe ? s ................................................................................................................. 75 inte ?? u ? t o ? e ? ation ................................................................................................................ 75 inte ?? u ? t p ? io ? ity ..................................................................................................................... 7 ? exte ? nal inte ?? u ? t ............. ...................................................................................................... 78 ti ? e ? /event counte ? inte ?? u ? t ............................................................................................... 80 ti ? e base inte ?? u ? t ............................................................................................................... 80 multi-function inte ?? u ? t .......................................................................................................... 81 co ?? a ? ato ? inte ?? u ? t ............................................................................................................. 81 eeprom inte ?? u ? t ............. ................................................................................................... 8 ? inte ?? u ? t wake-u ? function ................................................................................................... 8 ? p ? og ? a ?? ing conside ? ations ............. ................................................................................... 8 ? buzzer ............................................................................................................. 83 confguration options ................................................................................... 85 application circuits ........... ............................................................................ 86 instruction set ................................................................................................ 87 int ? oduction ........................................................................................................................... 87 inst ? uction ti ? ing .................................................................................................................. 87 moving and t ? ansfe ?? ing data ............................................................................................... 87 a ? ith ? etic o ? e ? ations ............................................................................................................ 87 logical and rotate o ? e ? ations ............. ................................................................................. 88 b ? anches and cont ? ol t ? ansfe ? ............................................................................................. 88 bit o ? e ? ations ....................................................................................................................... 88
rev. 0.00 4 ?e?te??e? ??? ?01? rev. 0.00 5 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators ta ? le read o ? e ? ations ......................................................................................................... 88 othe ? o ? e ? ations ............. ...................................................................................................... 88 inst ? uction ? et ? u ?? a ? y ....................................................................................................... 89 instruction defnition ..................................................................................... 91 package information ................................................................................... 100 1 ? - ? in n ? op (150 ? il) outline di ? ensions ......................................................................... 100 ? 0- ? in ?? op (150 ? il) outline di ? ensions ......................................................................... 101 reel di ? ensions ................................................................................................................. 10 ? ca ?? ie ? ta ? e di ? ensions ..................................................................................................... 103
rev. 0.00 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 7 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators features cpu features ? operating voltage: ? f sys = 910khz: 2.2v~5.5v ? f sys = 2mhz: 2.2v~5.5v ? f sys = 4mhz: 2.2v~5.5v ? f sys = 8mhz: 3.3v~5.5v ? f sys = 12 mhz: 4.5v~5.5v ? tiny power technology for low power operation ? power down and wake-up functions to reduce power consumption ? oscillator types: ? external crystal C hxt ? external rc C erc ? internal rc C hirc ? internal 32khz rc C lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 32khz, 910khz, 2mhz, 4mhz and 8mhz oscillator requires no external components ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 4-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 1k15 ? ram data memory: 648 ? eeprom memory: 328 ? watchdog t imer function ? up to 18 bidirectional i/o lines ? multiple pin-shared external interrupts ? single 8-bit programmable t imer/event counter with overfow interrupt ? dual t ime-base functions ? dual comparator functions ? dual operational amplifers functions ? pfd/buzzer for audio frequency generation ? internal 2.4v/3.3v ldo ? low voltage reset function ? package: 16-pin nsop , 20-pin ssop
rev. 0.00 ? ?e?te??e? ??? ?01? rev. 0.00 7 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators general description the d evice i s fl ash me mory t inypower t ype 8 -bit h igh p erformance r isc a rchitecture m icrocontroller. offering users the convenience of flash memory multi-programming features, this device also includes a wi de ra nge of func tions a nd fe atures. ot her m emory i ncludes a n a rea of ram da ta memory as well as an area of eeprom memory for storage of non-volatile data such as calibration data etc. analog features incl ude dua l operational ampli fers, dua l com parators and one inte rnal 2.4v or 3.3v ldo (low drop out) for voltage regulator . protective features such as an internal w atchdog timer and low v oltage reset ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt , erc, hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the unique hol tek t inypower t echnology a lso gi ves t he de vice e xtremely l ow c urrent c onsumption characteristics, an extremely important consideration in the present trend for low power battery powered applicati ons. the usual holtek mcu features such as power down and wake-up functions, oscillator options, programmable frequency divider , etc. combine to ensure user applications require a minimum of external components. the inclusion of fexible i/o programming features, t ime-base functions along with many other features e nsure t hat t he de vice wi ll fnd e xcellent use i n a pplications suc h a s e lectronic m etering, environmental monitoring, handhel d instruments, electronically controlled tools, motor driving and many others. block diagram the following block diagram illustrates the main functional blocks.
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rev. 0.00 8 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 9 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators pin assignment 1 ? 3 4 5 ? 7 8 9 10 ?0 19 18 17 1? 15 14 13 1? 11 ht 45 f 12 20 ssop -a pb ? pb 0/ int pb 3 pb ? pb 1 pa 1/c1 out / tmr pc ?/c?p pc 5/c1n pc 4/ vcap pa 0/ cnp pc 0/ o?c 1 pc 1/ o?c ? v?? vdd pa ?/a1p/c? out pa 3/a1n/ int 0 pa 4/a1e pa 5/a?p/ pfd pa ?/a?n/ bz pa 7/a?e/ bz ht 45 f 12 16 nsop -a pc 0/ o?c 1 pc 1/ o?c ? v?? vdd pa ?/a1p/c? out pa 3/a1n/ int 0 pa 4/a1e pa 5/a?p/ pfd 1 ? 3 4 5 ? 7 8 1? 15 14 13 1? 11 10 9 pb ? pa 1/c1 out / tmr pc ?/c?p pc 5/c1n pc 4/ vcap pa 0/ cnp pa 7/a?e/ bz pa ?/a?n/ bz
rev. 0.00 8 ?e?te??e? ??? ?01? rev. 0.00 9 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators pin description pin name function opt i/t o/t description pa0/cnp pa0 papu pawu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and wake-u ? . cnp cmp1c1 cmpi cmo ? co ?? a ? ato ? in ? ut ? in pa1/c1out / tmr pa1 papu pawu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and wake-u ? . c1out cmp1c1 cmpo co ?? a ? ato ? 1 out ? ut ? in tmr ? t exte ? nal ti ? e ? clock in ? ut pa ? /a1p/ c ? out pa ? papu pawu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and wake-u ? . a1p opa1c1 opai opa1 non-inve ? ting in ? ut ? in c ? out cmp ? c1 cmpo co ?? a ? ato ? ? out ? ut ? in pa3/a1n /int0 pa3 papu pawu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and wake-u ? . a1n opa1c1 opai opa1 inve ? ting in ? ut ? in int0 ? t exte ? nal inte ?? u ? t 0 in ? ut ? in pa4/a 1e pa4 papu pawu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and wake-u ? . a1e opa1c1 opao opa1 out ? ut ? in pa5/a ? p/pfd pa5 papu pawu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and wake-u ? . a ? p opa ? c1 opai opa ? non-inve ? ting in ? ut ? in pfd mi ? c cmo ? pfd out ? ut pa ? /a ? n/bz pa ? papu pawu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and wake-u ? . a ? n opa ? c1 opai opa ? inve ? ting in ? ut ? in bz bpctl cmo ? buzze ? out ? ut pa7/a ? e/ bz pa7 papu pawu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and wake-u ? a ? e opa ? c1 opao opa ? out ? ut ? in bz bpctl cmo ? co ?? le ? enta ? y ? uzze ? out ? ut pb0/int1 pb0 pbpu mi ? c ? t cmo ? nmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and out ? ut nmo ? st ? uctu ? e. int1 ? t exte ? nal inte ?? u ? t 1 in ? ut ? in pb1 pb1 pbpu mi ? c ? t cmo ? n mo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and out ? ut nmo ? st ? uctu ? e. pb ? pb ? pbpu mi ? c ? t cmo ? n mo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and out ? ut nmo ? st ? uctu ? e. pb3 pb3 pbpu mi ? c ? t cmo ? n mo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? and out ? ut nmo ? st ? uctu ? e. pb ? pb ? pbpu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? pc0/o ? c1 pc0 pcpu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? o ? c1 co hxt hxt/erc ? in pc1/o ? c ? pc1 pcpu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? o ? c ? co hxt hxt ? in pc4/vcap pc4 pcpu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? vcap ldoc ldo output capacitor pin. connect a 0.1f ca ? acito ? .
rev. 0.00 10 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 11 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators pin name function opt i/t o/t description pc5/c1n pc5 pcpu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? c1n cmp1c1 cmpi co ?? a ? ato ? 1 inve ? ting in ? ut ? in pc ? /c ? p pc ? pcpu ? t cmo ? gene ? al ? u ?? ose i/o. registe ? ena ? led ? ull-u ? c ? p cmp ? c1 cmpi co ?? a ? ato ? ? non-inve ? ting in ? ut ? in vdd vdd pwr powe ? su ?? ly v ?? v ?? pwr g ? ound note : i/t: input type o/t: output type opt: optional by confguration option (co) or register option pwr: power co: confguration option st: schmitt t rigger input cmos: cmos output nmos: nmos output hxt: high frequency crystal oscillator opai: operational amplifer input opao: operational amplifer output cmpi: comparator input cmpo: comparator output as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. absolute maximum ratings supply v oltage .......................................................................................................................... v ss -0.3v to v ss +6.0v input v oltage ............................................................................................................................ v ss -0.3v to v dd +0.3v i ol t otal ............................................................. 100ma total power dissipation .................................... 500mv storage t emperature .......................... -50c to 150c operating t emperature ...................... -40c to 150c i oh t otal ........................................................... -100ma note: these are stress ratings only . stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not impl ied and prolonged exposure to extreme conditions may af fect device reliability.
rev. 0.00 10 ?e?te??e? ??? ?01? rev. 0.00 11 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators d.c. characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd o ? e ? ating voltage f ? y ? = 910k hz ? (hxt/erc/hirc) ? . ? 5.5 v f ? y ? = ? mhz ? (hxt/erc/ hirc) ? . ? 5.5 v f ? y ? = 4mhz ? (hxt/erc/ ec/hirc) ? . ? 5.5 v f ? y ? = 8mhz ? (hxt/erc/ ec/hirc) 3.3 5.5 v f ? y ? = 1 ? mhz ? (hxt/erc/ ec) 4.5 5.5 v i dd1 o ? e ? ating cu ?? ent (hxt ? erc) 3.3v no load ? f ? y ? = f m = 455khz ? lvr off ? co ?? a ? ato ? off ? opas off 70 110 a no load ? f ? y ? = f m = 455khz ? lvr o n ? co ?? a ? ato ? o n ? opas off 100 150 a i dd ? o ? e ? ating cu ?? ent (erc ? hirc) 3.3v no load ? f m = 910khz ? f ? y ? = f ? low = 455khz ? lvr off ? co ?? a ? ato ? off ? opas off 90 135 a no load ? f m = 910khz ? f ? y ? = f ? low = 455khz ? lvr o n ? co ?? a ? ato ? o n ? opas off 1 ? 0 180 a i dd3 o ? e ? ating cu ?? ent (erc ? hirc) 3.3v no load ? f ? y ? = f m = 910khz ? lvr off ? co ?? a ? ato ? off ? opas off 110 170 a no load ? f ? y ? = f m = 910khz ? lvr on ? co ?? a ? ato ? o n ? opas off 1 ? 0 ? 40 a i dd4 o ? e ? ating cu ?? ent (erc ? hxt) 3.3v no load ? f ? y ? = f m = 1mhz ? lvr off ? co ?? a ? ato ? off ? opas off 1 ? 0 180 a no load ? f ? y ? = f m =1mhz ? lvr on ? co ?? a ? ato ? on ? opas off 170 ?? 0 a i dd5 o ? e ? ating cu ?? ent (hxt ? erc ? hirc) 3.3v no load ? f ? y ? = f m = ? mhz ? lvr off ? co ?? a ? ato ? off ? opas off 170 ?? 0 a no load ? f ? y ? = f m = ? mhz ? lvr on ? co ?? a ? ato ? on ? opas off ? 00 300 a i dd ? o ? e ? ating cu ?? ent (hxt ? erc ? hirc) 3v no load ? f ? y ? = f m = 4mhz 4 ? 0 ? 30 a 5v 700 1000 a i dd7 o ? e ? ating cu ?? ent ( ec ? ode ) 3v no load ? f ? y ? = f m = 4mhz 330 500 a 5v 550 8 ? 0 a i dd8 o ? e ? ating cu ?? ent (hxt ? erc ? hirc) 5v no load ? f ? y ? = f m = 8mhz 1.5 3.0 ? a i dd9 o ? e ? ating cu ?? ent (hxt ? erc) 5v no load ? f ? y ? = f m = 1 ? mhz ? .5 5.0 ? a i dd10 o ? e ? ating cu ?? ent ( ? low mode ? f m =4mhz) (hxt ? erc ? hirc) 3v no load ? f ? y ? = f ? low = 1mhz ? 00 300 a 5v 400 ? 00 a i dd11 o ? e ? ating cu ?? ent ( ? low mode ? f m =4mhz) (hxt ? erc ? hirc) 3v no load ? f ? y ? = f ? low = ? mhz ? 50 375 a 5v 5 ? 0 840 a i dd 1 ? o ? e ? ating cu ?? ent ( ? low mode ? f m =8mhz) (hxt ? erc ? hirc) 3v no load ? f ? y ? = f ? low = ? mhz 300 450 a 5v ? 80 10 ? 0 a i dd13 o ? e ? ating cu ?? ent ( ? low mode ? f m =8mhz) (hxt ? erc ? hirc) 3v no load ? f ? y ? = f ? low = 4mhz 450 800 a 5v 1000 1500 a i dd14 o ? e ? ating cu ?? ent (f ? y ? =f lirc ) 3v no load ? wdt off 10 ? 0 a 5v ? 0 35 a
rev. 0.00 1 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 13 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators symbol parameter test conditions min. typ. max. unit v dd conditions i ? tb1 ? tand ? y cu ?? ent ( ? lee ? ) (f ? y ? ? f ? ub ? f ? ? f wdt = off) 3v no load ? syste ? halt ? wdt off 0.1 1.0 a 5v 0. ? ? .0 a i ? tb ? ? tand ? y cu ?? ent ( ? lee ? ) (f ? y ? off ? f ? on ? f wdt = f ? ub = f lirc ) 3v no load ? syste ? halt ? wdt on ? 4 a 5v 4 ? a i ? tb3 ? tand ? y cu ?? ent (idle) (f ? y ? off ? f wdt off ? f ? = f ? ub = f lirc ) 3v no load ? syste ? halt ? wdt off 4 ? a 5v ? 9 a v il1 in ? ut low voltage fo ? i/o ? tmr ? int0 and int1 0 0.3v dd v v ih1 in ? ut high voltage fo ? i/o ? tmr ? int0 and int1 0.7v dd v dd v v il3 in ? ut low voltage (pb1~pb3) 5v 1 v v ih3 in ? ut low voltage (pb1~pb3) 5v ? v v lvr1 low voltage reset v lvr = ? .10v -5% ty ? . ? .10 -5% ty ? . v v lvr ? v lvr = ? . 55v ? .55 v lvr3 v lvr = 3.15v 3.15 v lvr4 v lvr = 3.80v 3.80 i ol i/o po ? t ? ink cu ?? ent 3v v ol = 0.1v dd ? 1 ? ? a 5v 10 ? 5 ? a i oh i/o po ? t ? ou ? ce cu ?? ent 3v v oh = 0.9v dd - ? -4 ? a 5v -5 -8 ? a r ph pull-high resistance 3v ? 0 ? 0 100 k 5v 10 30 50 k i lvr dc cu ?? ent when lvr tu ? n on lvr disa ? le lvr ena ? le 10 ? 0 a 15 30 a t lvr low voltage width to reset 1 ? 0 ? 40 480 s t ? re ? et ? oftwa ? e reset width to reset 45 90 1 ? 0 s note: t sub = 1/f sub
rev. 0.00 1? ?e?te??e? ??? ?01? rev. 0.00 13 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators a.c. characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd condition f ? y ? 1 ? yste ? clock (hxt ? erc ? hirc) ? . ? ~5.5v 400 4000 khz 3.3~5.5v 400 8000 khz 4.5~5.5v 400 1 ? 000 khz f ? y ? ? 8mhz hirc 3.3v ta= ? 5 c - ? % 8 + ? % mhz 3.3v ta= -40c~85c -5% 8 +5% mhz ? .7 ~5.5v ta= -40c~85c -10% 8 +10% mhz f ? y ? 3 4mhz hirc 3.3v ta= ? 5 c - ? % 4 + ? % mhz 3.3v ta= -40c~85c -5% 4 +5% mhz ? .7 ~5.5v ta= -40c~85c -10% 4 +10% mhz f ? y ? 4 ? mhz hirc 3.3v ta= ? 5 c - ? % ? + ? % mhz 3.3v ta= -40c~85c -5% ? +5% mhz ? .7 ~5.5v ta= -40c~85c -10% ? +10% mhz f ? y ? 5 910khz hirc 3.3v ta= ? 5 c - ? % 0.91 + ? % mhz 3.3v ta= -40c~85c -5% 0.91 +5% mhz ? .7 ~5.5v ta= -40c~85c -10% 0.91 +10% mhz f lirc ? yste ? clock ( lirc) 5v ta= ? 5 c -10% 3 ? +10% khz ? . ? ~5.5v ta= -40c to 85c -50% 3 ? + ? 0% khz t int inte ?? u ? t mini ? u ? pulse width 1 3.3 5 s t r ? td ? yste ? reset delay ti ? e (powe ? on reset) ? 5 50 100 ? s ? yste ? reset delay ti ? e (any reset exce ? t powe ? on reset) 8.3 1 ? .7 33.3 ? s t ?? t ? yste ? sta ? t-u ? ti ? e ? ? e ? iod (wake-u ? f ? o ? halt ? f ? y ? off at halt state) f ? y ? = hxt 1 ? 8 t ? y ? f ? y ? = erc o ? hirc 1 ? f ? y ? = lirc ? ? yste ? ? ta ? t-u ? ti ? e ? pe ? iod (wake-u ? f ? o ? halt ? f ? y ? on at halt state) ? note: t sys = 1/f sys .
rev. 0.00 14 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 15 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators op amplifer electrical characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions d.c. characteristic v dd o ? e ? ating voltage f f ? . ? f 5.5 v i dd quiescent cu ?? ent 5v no load f ? 00 350 v o po ? 1 in ? ut offset voltage 5v axof4~0= (10000) -15 f +15 ? v v o po ? ? in ? ut offset voltage 5v by cali ?? ation -4 f +4 ? v i o po ? in ? ut offset cu ?? ent f v dd = 5v ? v cm = 1/ ? v dd ? ta= -40 c~85c f 10 f na v cm co ?? on mode voltage range f f v ?? f v dd -1.4 v p ? rr powe ? ? u ?? ly rejection ratio f f 58 80 f db cmrr co ?? on mode rejection ratio f v dd = 5v v cm = 0~(v dd -1.4v) 58 80 f db a.c. characteristic a ol o ? en l oo ? gain f f ? 0 80 f db ? r ? lew rate + ? ra te - f no load f 0.1 f 9v gbw gain band width f r l 0 c l = 100 ? f 100k ? m f hz comparator electrical characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd condition v ddc co ?? a ? ato ? o ? e ? ating voltage f f ? . ? f 5.5 ? v i ddc co ?? a ? ato ? o ? e ? ating cu ?? ent 3.3v f f ? 0 40 a 5v f f 30 ? 0 a v cpo ? 1 co ?? a ? ato ? in ? ut offset voltage f cxof4~0=(10000) -10 f +10 ? v v cpo ? ? co ?? a ? ato ? in ? ut offset voltage f by cali ?? ation -4 f +4 ? v v cm co ?? a ? ato ? co ?? on mode voltage range f f v ?? f v dd -1.4v v aol co ?? a ? ato ? o ? en loo ? gain f f ? 0 80 f db t pd1 co ?? a ? ato ? res ? onse ti ? e f with ?? v ove ? d ? ive f f 10 s t pd ? co ?? a ? ato ? res ? onse ti ? e f with 10 ? v ove ? d ? ive f f 1.5 s
rev. 0.00 14 ?e?te??e? ??? ?01? rev. 0.00 15 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators ldo 2.4v electrical characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions v ddin ? u ?? ly voltage f f 3.0 3.3 3. ? v v ddout out ? ut voltage f f -5% ? .4 +5% v i dd cu ?? ent consu ?? tion f afte ? sta ? tu ?? no load f 30 f ldo 3.3v electrical characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions v ddin ? u ?? ly voltage f f 4.5 5 5.5 v v ddout out ? ut voltage f f -5% 3.3 +5% v i dd cu ?? ent consu ?? tion f afte ? sta ? tu ?? no load f 50 f power-on reset characteristics ta= 25c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd ? ta ? t voltage to ensu ? e powe ? -on reset 100 ? v rr vdd vdd raising rate to ensu ? e powe ? -on reset 0.035 v/ ? s t por mini ? u ? ti ? e fo ? vdd ? tays at v por to e nsu ? e powe ? -on reset 1 f f ? s
rev. 0.00 1 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 17 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantag e of the usual features found within ris c microcontrollers providing increas ed s peed of operation and enhanced performance. the pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution a re ove rlapped, he nce i nstructions a re e ffectively e xecuted i n one c ycle, wi th t he exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithm etic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addresse d. the simple addressi ng met hods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional i/o with maximum reliability and fexibility . this makes the device suitable for low-cost, high-volume production for controller applications clocking and pipelining the system clock, derived from eit her a crystal/resonator or rc oscillator is subdivided into four internally ge nerated non-ove rlapping c locks, t 1~t4.the progra m count er i s i ncremented a t t he beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively e xecuted i n o ne i nstruction c ycle. t he e xception t o t his a re i nstructions whe re t he contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two instruction cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
? ? ? ? ? system clocking and pipelining
rev. 0.00 1? ?e?te??e? ??? ?01? rev. 0.00 17 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators
? ? ? ? ? ? ? ? ? ? instruction fetching program counter C pc during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subroutine call, interrupt or reset, etc. the microcontroller manages program control by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc9~pc8 pcl7~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessible under program control. manipulating the pcl might cause program branchin g, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section.
rev. 0.00 18 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 19 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is or ganized into 4 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack.
if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost. arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti.
rev. 0.00 18 ?e?te??e? ??? ?01? rev. 0.00 19 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators flash program memory the program memory is the locatio n where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a lar ge number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, the flash device of fers users the fexibility to conveniently debug and develop their applications while also of fering a means of field programming and updating. structure the p rogram m emory has a capacity of 1 kx1 5 bits . the p rogram m emory is address ed by the program counter and also contains data, table information and interrupts entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. special vectors within the program memory, certain locations are reserved for the reset and interrupts. ? location 000h this vector is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. ? location 004h this vector is used by the external interrupt 0. if the external interrupt pin receives an active edge, t he program wi ll j ump t o t his l ocation a nd b egin e xecution i f t he e xternal i nterrupt i s enabled and the stack is not full. ? location 008h this vector is us ed by the external interrupt 1. if the external interrupt pin receives an active edge, the p rogram wi ll j ump t o t his l ocation a nd b egin e xecution i f t he e xternal i nterrupt i s enabled and the stack is not full. ? location 00ch this i nternal v ector i s u sed b y t he t imer/event c ounter. i f a t imer/event c ounter o verflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full . ? location 018h this internal vector is used by the multi-function interrupt. when the t ime base overflows, a comparator output interrupt, an eep rom w rite or read cycle ends interrupt, the program w ill jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full.
rev. 0.00 ? 0 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 ?1 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators initialisation vecto? exte?nal inte??u?t 1 vecto? exte?nal inte??u?t 0 vecto? ti?e?/event counte? inte??u?t vecto? rese?ved rese?ved multi-function inte??u?t vecto? look-u? ta?le (?5? wo?ds) look-u? ta?le (?5? wo?ds) note: n = 0 ~ 3 000h 004h 008h 00ch 010h 014h 018h n00h nffh 300h 3ffh p?og?a? me?o?y (10?4*15) 15-?it program memory structure look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the t abrdc[m] or t abrdl[m] instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defned data memory re gister [m ] as spe cified in the instruction. the hi gher orde r table da ta byte from the program me mory wi ll b e t ransferred t o t he t blh sp ecial r egister. an y u nused b its in t his transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.
rev. 0.00 ?0 ?e?te??e? ??? ?01? rev. 0.00 ? 1 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators

instruction table location b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [ ? ] pc9 pc8 @7 @ ? @5 @4 @3 @ ? @1 @0 tabrdl [ ? ] 1 1 @7 @ ? @5 @4 @3 @ ? @1 @0 table location note: b9~b0: t able location bits pc9~pc8: current program counter bits @7~@0: t able pointer tblp bits table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 3 00h which refers to the start address of the last page within the 1 k words program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 3 06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrdc [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the t abrdl [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
rev. 0.00 ?? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 ?3 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,07h ; initialise high table pointer mov tbhp,a : : tabrd c tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 3 06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd c tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 3 05h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 3 00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. mcu programming pins function data ? e ? ial data in ? ut/out ? ut clk ? e ? ial clock re ? device reset vdd powe ? ? u ?? ly v ?? g ? ound the program memory and eeprom data memory can both be programmed serially in-circuit using this 5-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for the clock. t wo additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. during t he progra mming proc ess t he res pi n wi ll be he ld l ow by t he progra mmer di sabling t he normal operation of the microcontroller and taking control of the p a0 and p a2 i/o pins for data and clock programmin g purposes. the user must take care to ensure that no other outputs are connected to these two pins.
rev. 0.00 ?? ?e?te??e? ??? ?01? rev. 0.00 ? 3 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators programmer pin mcu pins re ? pb ? data pa0 clk pa ? programmer and mcu pins
note: * may be resistor or capacitor . the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored.

? ? ?? ? ? ? - - data memory structure note: mo st o f t he da ta me mory b its c an b e d irectly m anipulated u sing t he se t [ m].i and c lr [ m]. i with the exception of a few dedicated bits. the data memory can also be accessed through the memory pointer registers.
rev. 0.00 ? 4 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 ?5 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locatio ns within this area are read and write accessible under program control. the r am da ta me mory i s su bdivided i nto 2 b ank s , k nown a s b ank 0 a nd b ank1 , t he sp ecial purpose data memory registers are accessible in all banks, with the exception of the eectrl register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory is the address 00h.

?? ? ? ? ? ? ? ? ?
??? ? ? ? ? ? ? ? ? ? ? ?? ?? ? ? ? ? ? ? ??? ?- ? ? ? ? ?? ?

? ? special purpose data memory
rev. 0.00 ?4 ?e?te??e? ??? ?01? rev. 0.00 ? 5 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 d b ? adres3 d b ? adres4 d b ? block db ? code .section at 0 code org00h start : mov a , 04h ; setup size of block mov block , a mov a , offset adres1 ; accumulator loaded with frst ram address mov mp0 , a ; setup memory pointer with frst ram address loop : clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 0.00 ?? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 ?7 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators bank pointer C bp the data memory is divided into two banks, known as bank 0 and bank 1. a bank pointer , which is bit 0 of the bank pointer register is used to select the required data memory bank. only data in bank 0 can be di rectly a ddressed , a s da ta i n ba nk 1 m ust be i ndirectly a ddressed usi ng me mory pointer mp1 and indirect addressing register iar1. using memory pointer mp0 and indirect addressing re gister iar0 wi ll a lways a ccess da ta from ba nk 0, i rrespective of t he va lue of t he bank pointer . memory pointer mp1 and indirect addressing register iar1 can indirectly address data in either bank 0 or bank 1 depending upon the value of the bank pointer. the data memory is initialised to bank 0 after a reset, except for the wdt time-out reset in the idle/ sleep mode, in which case, the data memory bank remains unaf fected. it should be noted that special function data memory is not af fected by the bank selection, which means that the special function registers can be accessed from within either bank 0 or bank 1. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. bp register bit 7 6 5 4 3 2 1 0 na ? e bp0 r/w r/w por 0 bit 7~1 unimplemented, read as "0" bit 0 bp0 : select data memory banks 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user defi ned regi ster and anot her, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter a nd i ndicates t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 0.00 ?? ?e?te??e? ??? ?01? rev. 0.00 ? 7 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller . with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 na ? e to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x "x" unknown bit 7 ~ 6 unimplemented, read as "0" bit 5 to : w atchdog t ime-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero
rev. 0.00 ? 8 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 ?9 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. system control register C ctrl this register is used to provide control over various internal functions. some of these include the certain system clock options, the lvr control, w atchdog t imer function. ctrl register bit 7 6 5 4 3 2 1 0 na ? e f ? y ? on lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 "x" unknown bit 7 fsyson : f control in idle mode 0: disable 1: enable bit 6~3 unimplemented, read as "0" bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software-reset function. this bit can only be cleared to 0 by the application program. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program.
rev. 0.00 ?8 ?e?te??e? ??? ?01? rev. 0.00 ? 9 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators eeprom data memory one of the s pecial features in the device is its internal eep rom d ata m emory. eep rom, w hich stands for electrically erasable programmable read only memory , is by its nature a non-volatile form of memory , with data retention even when its power supply is removed. by incorporating this kind of data mem ory, a whol e new host of appl ication possibi lities are ma de avail able to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specifc user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 32 8 bits. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped and is therefore not directly accessible in same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea ddr , the data register , eed ata and a single control register , eec trl . as both the eea ddr and eed ata registers are located in bank 0, they can be directly accessed in the same wa y as any other special function register . the eec trl register however , being located in bank1, cannot be directly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec trl control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp , set to the value, 01h, before any operations on the eec trl register are executed. eeprom control registers list name bit 7 6 5 4 3 2 1 0 eeaddr d4 d3 d ? d1 d0 eedata d7 d ? d5 d4 d3 d ? d1 d0 eectrl wten wt rden rd eeaddr register bit 7 6 5 4 3 2 1 0 na ? e d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~ 5 unimplemented, read as "0" bit 4 ~0 data eeprom address data eeprom address bit 4 ~ bit 0
rev. 0.00 30 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 31 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators eectrl register bit 7 6 5 4 3 2 1 0 na ? e wten wt rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3 wten : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wt : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the w en has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set hi gh by the applicat ion program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the w en, w , rden and rd can not be set to 1 at the same time in one instruction. the w and rd can not be set to 1 at the same time. eedata register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 data eeprom data data eeprom data bit 7 ~ bit 0
rev. 0.00 30 ?e?te??e? ??? ?01? rev. 0.00 31 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators reading data from the eeprom to re ad da ta fro m t he e eprom, t he re ad e nable bi t, rde n, i n t he e ectrl re gister m ust fi rst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eeaddr register . if the rd bit in the eectrl register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eeda ta register . the data will remain in the eeda ta register until another read or w rite operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom to write data to the eeprom, the write enable bit, w t en, in the eectrl register must frst be set high to enable the write functio n. the eeprom address of the data to be written must then be placed in the eeaddr register and the data placed in the eeda ta register . if the w t bit in the eectrl register is now set high, an internal write cycle will then be initiated. setting the w t bit high will not initi ate a write cycle if the w t en bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the w t bit in the eectrl register or by usi ng t he e eprom i nterrupt. w hen t he wri te c ycle t erminates, t he w t bi t wi ll be automatically c leared t o z ero by t he m icrocontroller, i nforming t he use r t hat t he da ta ha s be en written to the eeprom. the applic ation program can therefore poll the w t bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write or read interrupt is generated when an eeprom write or read cycle has ended. the eeprom interrupt must frst be enabled by setting the e2i bit in the relevant interrupt register . however as the eeprom is contained within a multi-function interrupt, the associated multi- function interrupt enable bit must also be set. when an eeprom write cycle ends, the e2f request fag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi-function interrupts are enabled and the stack is not full, a jump to the associated multi- function interrupt vector wi ll take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section.
rev. 0.00 3 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 33 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. the w t bit in the eectrl register should be set immediate ly after the w t en bit is set, otherwise the eeprom write cycle will not be executed. programming examples ? reading data from the eeprom C polling method mov a, eeprom_adres ; user defned address mov eeaddr, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eectrl register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr bp mov a, eedata ; move read data to register mov read_data, a ? writing data to the eeprom - polling method mov a, eeprom_adres ; user defned address mov eeaddr, a mov a, eeprom_data ; user defned data mov eedata, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eectrl register mov a, 01h ; setup bank pointer mov bp, a set iar1.3 ; set w en bit, enable write operations set iar1.2 ; start write cycle - set w sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr bp
rev. 0.00 3? ?e?te??e? ??? ?01? rev. 0.00 33 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase f unctions. e xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are pr ovided t o fo rm a wi de ra nge of bo th fa st a nd sl ow syst em osc illators. al l osc illator op tions are se lected t hrough t he c onfiguration o ptions. t he hi gher fr equency o scillators pr ovide hi gher performance b ut c arry wi th i t t he d isadvantage o f h igher p ower r equirements, wh ile t he o pposite is of course true for the lower frequency osc illators. w ith the capabil ity of dynamicall y switching between fas t and s low s ystem clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. type name freq. pins exte ? nal c ? ystal hxt 400khz~ 1 ? mhz o ? c1/o ? c ? exte ? nal rc erc 910khz ? ? mhz ? 4mhz o ? c1 exte ? nal clock ec 400khz~ 1 ? mhz o ? c1 inte ? nal high ?? eed rc hirc 910khz ? ? /4/8mhz inte ? nal low ?? eed rc lirc 3 ? khz oscillator types system clock confgurations there are f ive methods of generating the system clock, four high speed oscillators and one low speed oscillators. the high speed oscillators are the external crystal/ceramic oscillator , external rc network o scillator, e xternal c lock a nd t he i nternal 9 10khz, 2 mhz, 4 mhz o r 8 mhz r c o scillator. the one low speed oscillators is the internal 32khz rc oscillator.

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rev. 0.00 34 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 35 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and l cks2~ l cks0 bits in the s ys mod register and as the system clock can be dynamicall y selected. the actual source clock used for each of the high speed and low speed oscillators i s c hosen v ia c onfiguration o ptions. t he f requency o f t he sl ow sp eed o r h igh sp eed system clock is also determined using the hlclk bit and l cks2~l cks0 bits in the s ys mod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. external crystal/ceramic oscillator C hxt the e xternal cryst al/ceramic syst em osc illator i s one of t he hi gh fre quency osc illator c hoices, which is s elected via configuration option. f or mos t crystal os cillator configurations, the s imple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring extern al capacitors. however , for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation.
? ? ?? crystal/resonator oscillator C hxt crystal oscillator c1 and c2 values crystal frequency c1 c2 1 ? mhz 0 ? f 0 ? f 8mhz 0 ? f 0 ? f 4mhz 0 ? f 0 ? f 1mhz 100 ? f 100 ? f note: c1 and c ? values a ? e fo ? guidance only. crystal recommended capacitor values
rev. 0.00 34 ?e?te??e? ??? ?01? rev. 0.00 35 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators external rc oscillator C erc using the erc oscillator only requires that a resistor , with a value between 56 k and 2.4m, is connected between osc1 and vdd, and a capacitor is connected between osc1 and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for st ability purpose s onl y. de vice t rimming duri ng t he m anufacturing proc ess a nd t he i nclusion of internal frequency compensation circuit s are use d to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. here only the osc1 pin is used, which is shared with i/o pin p c 0, leaving pin p c 1 free for use as a normal i/o pin. external rc oscillator C erc external oscillator C ec the system clock can also be supplied by an externally supplied clock giving users a method of synchronising t heir e xternal h ardware t o t he m icrocontroller o peration. t his i s se lected u sing a configuration opt ion a nd suppl ying t he c lock on pi n osc1 . pi n osc2 shoul d be l eft fl oating if t he external osc illator i s use d. t he i nternal osc illator c ircuit c ontains a fi lter c ircuit t o re duce the possibility of e rratic opera tion due t o noise on t he osc illator pi n, howe ver a s t he fl ter c ircuit consumes a certai n amount of power , a confguration option exists to turn this flter of f. not using the internal filter should be considered in power sensitive applications and where the externally supplied clock is of a high integrity and supplied by a low impedance source. internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc osc illator ha s four fi xed fre quencies of e ither 910khz , 2mhz , 4mhz or 8mhz . device trimming duri ng t he m anufacturing proc ess a nd t he i nclusion of i nternal frequenc y compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. note that if this internal system clock option is selected, as it requires no external pins for its operatio n, i/o pins pc0 and pc1 are free for use as normal i/o pins. internal 32khz oscillator C lirc the internal 32khz system oscillator is a low frequency oscillator . it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v , requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised.
rev. 0.00 3 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 37 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red port able a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided the device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the m ain sy stem c lock, c an c ome f rom e ither a h igh f requency, f h , o r l ow f requency, f l , so urce, and is selected using the hlclk bit and lcks2~l cks0 bits in the s ys mod register . the high speed system clock can be sourced from either an hxt , erc, ec or hirc oscillator , selected via a confguration option. the low speed system clock source can be sourced from internal clock lirc . the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power r equirements o f t he a pplication.there a re two m odes a llowing n ormal o peration o f t he microcontroller, the n ormal m ode and s low m ode.the remaining four modes , the s leep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched of f to conserve power.
rev. 0.00 3? ?e?te??e? ??? ?01? rev. 0.00 37 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators

? ? ? ? ? ? ? ? ? ? ?? ? ?? ? ? ? ? ?? ? ? - ? ? ? ? ? ? ? ? - ? ? ?? ? ? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ?? ? ? ?? ?? ?? ? ? ? - ? ? system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. operation mode descriptions cpu f sys f sub f s f tbc no ?? al ? ode on f h ~ f h / ? 4 on on on ? low ? ode on f l on on on idle0 ? ode off off on on on idle1 ? ode off on on on on ? leep0 ? ode off off off off off ? leep1 ? ode off off on on off
rev. 0.00 38 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 39 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operate s allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt , erc , ec or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the lcks2~l cks0 and hlclk bits in the s ys mod register . although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. the clock source used will be from the low speed oscillator , the lirc. running the microcontroller i n t his m ode a llows i t t o r un wi th m uch l ower o perating c urrents. i n t he sl ow mode, the f h is off. sleep0 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the sysmod register is low . in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the w atchdog t imer function is disabled. sleep1 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the sysmod register is low . in the sleep1 mode the cpu will be stopped. however the f sub and f s clocks will continue to operate if the w atchdog t imer function is enabled . idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the sys mod register is high and the fsyson bit in the ctrl register is low . in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the w atchdog t imer and t ime base. in the idle0 mode, the w atchdog t imer clock f s will be on . idle1 mode the idle1 mode is entered when an hal t instruction is executed and when the idlen bit in the s ys mod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the w atchdog t imer and t ime base . in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the w atchdog t imer clock f s will be on.
rev. 0.00 38 ?e?te??e? ??? ?01? rev. 0.00 39 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators control register a single register, s ys mod, is used for overall control of the internal clocks within the device. sysmod register bit 7 6 5 4 3 2 1 0 na ? e l ck ?? l ck ? 1 l ck ? 0 f ? ten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 : the system clock selection when hlclk is 0 000: f l (f lirc ) 001: f l (f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fast w ake-up control (only for hxt) 0:disable 1:enable this i s t he fa st w ake-up c ontrol b it wh ich d etermines i f t he f sub c lock so urce i s initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temp orary system clock to provide a faster wake up time as the f sub clock is available. bit 3 : lirc system osc sst ready fag 0: not ready 1: ready this is the low speed system oscill ator sst ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep 0 mode but after a wake-up has occurred, the fag will change to a high level after 1~2 clock cycles if the lirc oscillator is used. bit 2 : hirc system osc sst ready fag 0: not ready 1: ready this is the high speed system oscil lator sst ready flag which indicat es when the high speed s ystem os cillator is s table after a w ake-up has occurred. the flag w ill be low when in the sleep or idle 0 mode but after power on reset or a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the erc or hirc oscillator is used. bit 1 : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he idle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o keep t he pe ripheral fun ctions ope rational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed.
rev. 0.00 40 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 41 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power . to minimise power consumption the device can enter the sleep or idle 0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to re sume. t o e nsure t he de vice i s up a nd runni ng a s fa st a s possi ble a fa st w ake-up func tion i s provided, which allows f sub , namely lirc oscillator , to act as a temporary clock to frst drive the system until the original s ystem os cillator has s tabilised. a s the clock s ource for the f ast w ake- up functi on is f sub , the fast w ake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep 0 mode, the fast w ake-up function has no ef fect because the f sub clock is stopped. the fast w ake-up enable/disable function is controlled using the fsten bit in the s ys mod register. if the hxt oscil lator is sel ected as the normal mode syste m cl ock, and if the fa st w ake-up function is enabled, then it will take one to two t sub clock cycles of the lirc oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hx t clock cycles have elapsed, at which point the ht o fag will switch high and the system will switch over to operating from the hxt oscillator. if the erc or hirc oscillators or lirc oscillator is used as the system oscillator then it will take 15~16 clock cycle s of the erc or hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle 0 mode. the fast w ake-up bit, fsten will have no effect in these cases. fsten (sleep0 mode) (sleep1 mode) (idle0 mode) (idle mode) hxt 0 10 ? 4 hxt cycles 10 ? 4 hxt cycles 1~ ? hxt cycles 1 10 ? 4 hxt cycles 1~ ? f ? ub cycles ( ? yste ? ? uns with f ? ub frst for 10 ? 4 hxt cycles and then switches ove ? to ? un with the hxt clock) 1~ ? hxt cycles erc 15~1 ? erc cycles 15~1 ? erc cycles 1~ ? erc cycles ec 15~1 ? ec cycles 15~1 ? rc cycles 1~ ? ec cycles hirc 15~1 ? hirc cycles 15~1 ? hirc cycles 1~ ? hirc cycles lirc 1~ ? lirc cycles 1~ ? lirc cycles 1~ ? lirc cycles wake-u? ti?es note t hat t here i s no fa st st art-up fun ction whe n t he de vice i s i n sl eep m ode wi th t he w dt i s disabled. w e turn of f the regulator in this case. it will take 500s at most to become stable for regulator waked up from sleep mode.
rev. 0.00 40 ?e?te??e? ??? ?01? rev. 0.00 41 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators operating mode switching and wake-up the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and lcks2~l cks0 bits in the s ys mod register while mode switching from the normal/slow modes to the sleep /idle mode is executed via the h alt ins truction. when a hal t instructio n is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the s ys mod register and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other inte rnal functions. the accom panying fowchart shows what happens when the device moves between the various operating modes.

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normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the lcks2~l cks0 bits to 000 or 001 in the s ys mod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires the oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the s ys mod register.
rev. 0.00 4 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 43 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators
? ?? ?? ??? ? ?? ?? ??? ? ? - ? ?? ?? ??? ? ? - ? ?? ?? ???
? ? ?? ? ? ? ?? ? ? ? ? ?? ? ? ? ?? ? ? - ? ? ?? ? ? ???? ? - ? ? ?? ? ? ? ?? ?
rev. 0.00 4? ?e?te??e? ??? ?01? rev. 0.00 43 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators slow mode to normal mode switching in slow mode the system uses the lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0, but lcks2~l cks0 is set to 010, 01 1, 100, 101, 1 10 or 1 11. as a cert ain amount of time will be required for the high frequency clock to stabilise, the status of the ht o bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep0 mod e there is only one way for the devic e to enter the sleep0 mode and that is to execute the hal t instruction in the application program with the idlen bit in sys mod register equal to 0 and the wdt is off. when this instruction is executed under the conditions described above, the following will occur: the syst em cl ock, wdt cl ock and t ime base cl ock will be st opped and the appl ication program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the sleep 1 mode there i s on ly on e wa y f or t he de vice t o e nter t he sleep1 mo de a nd t hat i s t o e xecute t he halt instruction in the application program with the idlen bit in s ys mod register equal to 0 and the wdt is on. when this instruction is executed under the conditions described above, the following will occur : ? the system clock and t ime base clock will be stopped and the application program will stop at the halt instruction, but the wdt will remain with the clock source coming from the f l clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction in the application program with the idlen bit in s ys mod register equal to 1 and the fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the time base clock and f sub clock will be on . ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 0.00 44 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 45 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction in the application program with the idlen bit in s ys mod register equal to 1 and the fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock and f sub clock will be on and the application program will stop at the halt instruction ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled regardless of the wdt clock source which originates from the f l clock ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to device which ha s dif ferent package types, as there may be unbonded pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro- amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the halt instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status.
rev. 0.00 44 ?e?te??e? ??? ?01? rev. 0.00 45 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wi ll resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled. watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal clock, f s , which is in turn supplied by the lirc oscillato r. the lirc internal oscillator has an approximate period of 32 khz at a supply voltage of 5v . however , it should be noted that this specifed internal clock period can vary with v dd , tem perature and process varia tions. the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer tim eouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. this register together with several confguration options control the overall operation of the w atchdog t imer. wdtc register bit 7 6 5 4 3 2 1 0 na ? e we4 we3 we ? we1 we0 w ?? w ? 1 w ? 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7 ~ 3 : wdt enable bit if the wdt confguration option is selected as always enabled: 10101 or 01010: enabled other: reset mcu if the wdt confguration option is selected as application program enabled: 10101: disabled 01010: enabled other v alues: reset mcu if these bits are changed due to adverse environmental conditions, the microcontroller will be reset. the reset operation will be activated after 2~3 lirc clock cycles and the wr f bit in the ctrl register will be set to 1.
rev. 0.00 4 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 47 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators bit 2 ~ 0 ws2 ~ ws0 : select wdt t imeout period 000: 2 8 /f s 001: 2 10 /f s 010: 2 12 /f s 011: 2 14 /f s 100: 2 15 /f s 101: 2 16 /f s 110: 2 17 /f s 111: 2 18 /f s these three bits determine the divis ion ratio of the w atchdog t imer s ource clock, which in turn determines the timeout period. na ? e f ? y ? on lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson : f sys control in idle mode describe elsewhere. bit 6~3 unimplemented, read as 0 bit 2 lvrf : lvr function reset fag describe elsewhere. bit 1 lrf : lvr control register software reset fag describe elsewhere. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. a w atchdog timer c onfguration o ption d etermines i f t he w atchdog t imer i s a lways e nabled o r i f i t i s e nabled using the application program. w ith regard to the w atchdog t imer enable/disable function, there are also fve bits, we4~we0, in the wdtc register to of fer additional enable/disable and reset control of t he w atchdog t imer. if t he w dt c onfiguration opt ion ha s se lected t hat t he w dt func tion i s always enabled, then we4~we0 bits still have ef fect on the wdt function. when the we4~we0 bits value are equal to 01010b or 10101b, the wdt function is enabled. however, if the we4~we0 bits are changed to any other values except 01010b and 10101b, which could be caused by adverse environmental c onditions suc h a s noi se, i t wi ll re set t he m icrocontroller a fter 2~3 l irc c lock cycles. if the wdt confguration option has selected that the wdt function is controlled using the application program, then the wdt control register bits, we4~we0, are used to enable or disable the w atchdog t imer. in this case the wdt function will be disabled when the we4~we0 bits are
rev. 0.00 4? ?e?te??e? ??? ?01? rev. 0.00 47 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators equal to 10101b and enabled if the we4~we0 bits are equal to 01010b. if the we4~we0 bits are set to any other values, other than 01010b and 10101b, it will reset the device after 2~3 lirc clock cycles. after power on these bits will have a value of 01010b. wdt confguration option we4~we0 bits wdt function always ena ? led 01010b o ? 10101b ena ? le any othe ? value reset mcu a ?? lication p ? og ? a ? ena ? led 10101b disa ? le 01010b ena ? le any othe ? value reset mcu x: dont ca ? e. watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. for some low power consumption applications, it is recommended to disable the wdt function before entering the power down mode. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is an external hardware reset, the second is using the watchdog t imer software clear instruction and the third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt contents. the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. ? clr wdt ? inst?uction 8- stage divide? wdt p?escale? we 4~ we 0 ?its wdtc registe? reset mcu lirc f ? f ? /? 8 8- to - 1 mux clr w? ?~ w? 0 (f ? /? 8 ~ f ? /? 18 ) wdt ti?e - out (? 8 /f ? ~ ? 18 /f ? ) watchdog timer
rev. 0.00 48 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 49 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset, is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are four ways in which a microcontroller reset can occur , through events occurring both internally and externally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time= 50ms power-on reset timing chart low voltage reset C lvr the mi crocontroller cont ains a low volt age reset circui t in orde r to moni tor the supply volt age of the devic e . the l vr function has a specifc l vr voltage v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changi ng the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be set to 1 . t he l vr i ncludes t he fol lowing spe cifcations: for a va lid l vr si gnal, a l ow vol tage, i .e., a voltage in the range betw een 0.9v ~v lvr mus t exist for greater than the value t lvr s pecifed in the a.c. c haracteristics. if t he l ow vol tage st ate doe s not e xceed t lvr , t he l vr wi ll i gnore i t a nd wi ll not perform a reset function. one of a range of specifed voltage value s for v lvr can be selected by the l vs bits in the l vrc register . if the l vs7~lvs0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the l vr will reset the device after 2~3 lirc clock cycles. w hen this happens, the lrf bit in the ctrl register will be set to 1. after power on the register will have the value of 01010101b. note that the l vr function will be automatically disabled when the device enters the power down mode.
rev. 0.00 48 ?e?te??e? ??? ?01? rev. 0.00 49 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators note: t rstd is power-on delay, typical time= 16.7ms low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 na ? e lv ? 7 lv ?? lv ? 5 lv ? 4 lv ? 3 lv ?? lv ? 1 lv ? 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 : lvr voltage select 01010101: 2.1v (default) 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v other values: generates mcu reset C register is reset to por value when an actual low voltage condition occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles . in this s ituation the regis ter contents w ill remain the same after such a reset occurs. any register value , other than the four defned register values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation the register contents will be reset to the por value. ? ctrl register bit 7 6 5 4 3 2 1 0 na ? e f ? y ? on lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 : f sys control in idle mode describe elsewhere. bit 6~3 unimplemented, read as 0 bit 2 : lvr function reset fag 0: not occurred 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 : lvr control register software reset fag 0: not occurred 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 : wdt control register software reset fag describe elsewhere.
rev. 0.00 50 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 51 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a hardware power -on reset except that the w atchdog time-out fag t o will be set to 1. note: t rstd is power-on delay, typical time= 16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. note: the t sst is 16 clock cycles if the system clock source is provided by erc or hirc. the t sst is 128 clock for hxt . the t sst is 1~2 clock for lirc. wdt time-out reset during sleep or idle timing chart reset initial conditions the dif ferent types of res et des cribed af fect the res et fags in dif ferent ways. thes e fags , know n as pdf and t o are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or w atchdog t imer. the reset flags are shown in the table: to pdf reset conditions 0 0 powe ? -on ? eset u u lvr ? eset du ? ing normal o ? ? low mode o ? e ? ation 1 u wdt ti ? e-out ? eset du ? ing normal o ? ? low mode o ? e ? ation 1 1 wdt ti ? e-out ? eset du ? ing idle o ? ? leep mode o ? e ? ation note: u stands for unchanged the following table indicates the w ay in w hich the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset p ? og ? a ? counte ? reset to ze ? o inte ?? u ? ts all inte ?? u ? ts will ? e disa ? led wdt clea ? afte ? ? eset ? wdt ? egins counting ti ? e ? /event counte ? ti ? e ? counte ? will ? e tu ? ned off in ? ut/out ? ut po ? ts i/o ? o ? ts will ? e setu ? as in ? uts ? tack pointe ? ? tack pointe ? will ? oint to the to ? of the stack the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know wh at c ondition t he m icrocontroller i s i n a fter a p articular r eset o ccurs. t he f ollowing t able describes how eac h type of reset af fects the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type.
rev. 0.00 50 ?e?te??e? ??? ?01? rev. 0.00 51 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators register power-on reset wdt time-out (normal operation) lvr reset (normal operation) lvr reset ( halt ) wdt time-out ( halt) tmr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu tbhp ---- --xx ---- --uu ---- --uu ---- --uu ---- --uu ? tatu ? --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu mfic0 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu mfic1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb -1-- 1111 -1-- 1111 -1-- 1111 -1-- 1111 -u-- uuuu pbc -1-- 1111 -1-- 1111 -1-- 1111 -1-- 1111 -u-- uuuu pc -111 --11 -111 --11 -111 --111 -111 --11 -uuu --uu pcc -111 --11 -111 --11 -111 --11 -111 --11 -uuu --uu pawu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pbpu -0-- 0000 -0-- 0000 -0-- 0000 -0-- 0000 -u-- uuuu pcpu -000 --00 -000 --00 -000 --00 -000 --00 -uuu --uu ? y ? mod 0000 0x11 0000 0x11 0000 0x11 0000 0x11 uuuu uuuu intedge ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu mi ? c 0000 ---0 0000 ---0 0000 ---0 0000 ---0 uuuu ---u ldoc ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu lvrc 0101 0101 0101 0101 0101 0101 0101 0101 uuuu uuuu cmp1c0 0001 0000 0001 0000 0001 0000 0001 0000 uuuu uuuu cmp1c1 1--- 0010 1--- 0010 1--- 0010 1--- 0010 u--- uuuu cmp ? c0 0001 0000 0001 0000 0001 0000 0001 0000 uuuu uuuu cmp ? c1 00-- 0010 00-- 0010 00-- 0010 00-- 0010 uu-- uuuu opa1c0 0001 0000 0001 0000 0001 0000 0001 0000 uuuu uuuu opa1c1 0000 1100 0000 1100 0000 1100 0000 1100 uuuu uuuu opa ? c0 0001 0000 0001 0000 0001 0000 0001 0000 uuuu uuuu opa ? c1 0000 1100 0000 1100 0000 1100 0000 1100 uuuu uuuu opa ? c ? 00-- 0000 00-- 0000 00-- 0000 00-- 0000 uu-- uuuu ctrl 0--- -x00 0--- -x00 0--- -x00 0--- -x00 u--- -uuu wdtc 0101 0011 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 -111 0011 -111 0011 -111 0011 -111 uuuu -uuu bpctl ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu note: - not implement u stands for unchanged x stands for unknown
rev. 0.00 5 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 53 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names p a ~ p c . these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pawu d7 d ? d5 d4 d3 d ? d1 d0 papu d7 d ? d5 d4 d3 d ? d1 d0 pa d7 d ? d5 d4 d3 d ? d1 d0 pac d7 d ? d5 d4 d3 d ? d1 d0 pbpu d ? d3 d ? d1 d0 pb d ? d3 d ? d1 d0 pbc d ? d3 d ? d1 d0 pcpu d ? d5 d4 d1 d0 pc d ? d5 d4 d1 d0 pcc d ? d5 d4 d1 d0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. t o eliminate the need for these external resistors, when confgured as an input have the capabilit y of being connected to an internal pull-high resistor . these pull-high resistors are selected using registers papu ~pc pu, and are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~0 port a bit7~ bit 0 pull-high control 0: disable 1: enable
rev. 0.00 5? ?e?te??e? ??? ?01? rev. 0.00 53 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators pbpu register bit 7 6 5 4 3 2 1 0 na ? e d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 port b bit 6 pull-high control 0: disable 1: enable bit 5~4 unimplemented, read as "0" bit 3 ~0 port b bit 3 ~ bit 0 pull-high control 0: disable 1: enable pcpu register bit 7 6 5 4 3 2 1 0 na ? e d ? d5 d4 d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6~4 port c bit 6~4 pull-high control 0: disable 1: enable bit 3~2 unimplemented, read as "0" bit 1~0 port c bit 1 ~0 pull-high control 0: disable 1: enable port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 : port a bit 7 ~ bit 0 w ake - up control 0: disable 1: enable
rev. 0.00 54 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 55 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators i/o port control registers each i/o port has its own control register known as p ac ~ p c c, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 na ? e d7 d ? d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 : port a bit 7 ~ bit 0 input/output control 0: output 1: input pbc register bit 7 6 5 4 3 2 1 0 na ? e d ? d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 bit 7 unimplemented, read as "0" bit 6 : port b bit 6 input/output control 0: output 1: input bit 5~4 unimplemented, read as "0" bit 3~0 : port b bit 3 ~0 input/output control 0: output 1: input pcc register bit 7 6 5 4 3 2 1 0 na ? e d ? d5 d4 d1 d0 r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 bit 7 unimplemented, read as "0" bit 6~4 : port c bit 6~4 input/output control 0: output 1: input bit 3~2 unimplemented, read as "0" bit 1~0 : port c bit 1~0 input/output control 0: output 1: input
rev. 0.00 54 ?e?te??e? ??? ?01? rev. 0.00 55 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators misc register bit 7 6 5 4 3 2 1 0 na ? e ode3 ode ? ode1 ode0 pfden r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ode3 : pb3 open drain control 0: disable 1: enable bit ode2 : pb2 open drain control 0: disable 1: enable bit 5 ode1 : pb 1 open drain control 0: disable 1: enable bit 4 ode0 : pb 0 open drain control 0: disable 1: enable bit 3~1 unimplemented, read as 0 bit 0 pfden : pfd related control - described elsewhere i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.
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rev. 0.00 5 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 57 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac ~pc c, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, p a ~ p c , are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register o r b y p rogramming i ndividual b its i n t he p ort c ontrol r egister u sing t he set [ m].i a nd clr [m ].i i nstructions. not e t hat when usi ng t hese bi t c ontrol i nstructions, a re ad-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
read modify write timing port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. in addition, the p ort b pins als o provide o pen d rain i/o s tructure options w hich can be controlled by the specifc register. timer/event counter the provision of timers form an important part of any microcontroller , giving the designer a means of carrying out tim e related functio ns. the device contain s a sigle count-up timer of 8-bit capacity . as the tim er has three dif ferent operating modes, it can be confgured to operate as a general timer , an extern al event counter or as a pulse width capture device. the provision of an internal prescaler to the clock circuitry on giving added range to the timer. there are two types of registers related to the t imer/event counter . the frst is the register s that contain the actual value of the t imer/event counter and into which an initial value can be preloaded. reading from these registers retrieves the contents of the t imer/event counter . the second type of associated register is the t imer control register which defnes the timer options and determines how the t imer/event counter is to be used. the t imer/event counter can have its clock confgured to come from an internal clock source. in addition, its clock source can also be confgured to come from an external timer pin.

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? ? ? ? ?? 8-bit timer/event counter structure note : the output is controlled by pa5 data.
rev. 0.00 5? ?e?te??e? ??? ?01? rev. 0.00 57 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators timer control register C tmrc the fexible features of the holtek microcontroller t imer/event counter enable s it to operate in four different modes, the options of which are determined by the contents of its control register. it i s t he t imer cont rol re gister t ogether wi th i ts c orresponding t imer re gister control s t he ful l operation of the t imer/event counter . before the timer can be used, it is essential that the appropriate t imer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation to choose which of the four modes the timer is to operate in, either in the timer mode, the external event counting mode, the internal event counter mode, or the pulse width measurement mode, bits 7 and 6 o f t he t imer c ontrol r egister, whi ch is k nown a s t he b it p air t m1/ t m0 , must b e se t t o the required logic levels . the timer-on bit, which is bit 4 of the t imer control register and known as t on , provides the basic on/of f control of the timer . setting the bit high allows the counter to run, clearing the bit stops the counter . for the timer that ha s prescaler , bits 0~2 of the t imer control register determine the division ratio of the input clock prescaler . the prescaler bit settings have no ef fect if an external clock source is used. if the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the timer control register which is known as te . tmrc register bit 7 6 5 4 3 2 1 0 na ? e tm1 tm0 ton te tp ? c ? tp ? c1 tp ? c0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 bit 7 ~ 6 : t imer operation mode selection 00: event counter mode , the input signal is from comparator 1 output 01: event counter mode , the input signal is from t mr pin 10: t imer mode 11: pulse width capture mod e bit 5 u nimplemented, read as 0 bit 4 : t imer/event counter counting enable 0: disable 1: enable bit 3 : event counter active edge selection 1: count on falling edge 0: count on rising edge pulse w idth capture active edge selection 1: start counting on rising edge, stop on falling edge 0: start counting on falling edge, stop on rising edge bit 2~0 : t imer prescaler rate selection timer internal clock 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: f sys /128
rev. 0.00 58 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 59 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators confguring the timer mode in this mode, the t imer/event counter can be utilised to measure fxed time intervals, providing an internal interrupt signal each time the t imer/event counter overflows. t o operate in this mode, the operating mode select bit pair, tm1/tm0, in the t imer control register must be set to the correct value as shown . bit7 bit6 1 0 control register operating mode select bits for the t imer mode in this mode the internal clock is used as the timer clock. the timer input clock source is f sys oscillator. however , this timer cloc k source is further divided by a prescaler , the value of which is determined by the bits tps c2~tpsc 0 in the t imer control register . the timer -on bit, t on must be set high to enable the timer to run. each time an internal clock high to low transition occurs, the timer increments by one. when the timer is full and overfow s, an interrupt sigal is generated and t he t imer wi ll re load t he va lue a lready l oaded i nto t he pre load re gister a nd c ontinue c ounting. the interrupt can be disabled by ensuring that the timer/event counter interrupt e nable bit in the interrupt control register, intc0, is reset to zero.
timer mode timing chart confguring the event counter mode in this mode, a number of externally changing logic events, occurring on the internal comparators output, can be recorded by the t imer/event counter . t o operate in this mode, the operating mode select bit pair, tm1/tm0, in the t imer control register must be set to the correct value as shown. bit7 bit6 0 0/1 control register operating mode select bits for the event counter mode mode. in this mode, the comparator output, cmp1 op , is used as the t imer/event counter clock source, however it is not divided by the inte rnal prescaler . after the other bits in the t imer control register have been setup, the enable bit t on, which is bit 4 of the t imer control register , can be set high to enable the t imer/event counter to run. if the active edge select bit te, which is bit 3 of the t imer control r egister, i s l ow, t he t imer/event c ounter wi ll i ncrement e ach t ime the e xternal t imer p in receives a low to high transition. if the active edge select bit is high, the counter will increment each time the exte rnal timer pin receives a high to low transition. when it is full and overfows, an interrupt signal is generated and the t imer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disable d by ensuring that the t imer/ event count er interrupt ena ble bit i n t he interrupt cont rol register , intc0, i s rese t t o ze ro. it should be noted that in the internal event counting mode, even if the microcontroller is in the power down mode, the t imer/event counter will continue to record externally changing logic events on the timer input pin. as a result when the timer overfows it will generate a timer interrupt and corresponding wake-up source.
rev. 0.00 58 ?e?te??e? ??? ?01? rev. 0.00 59 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators event counter mode timing chart (te= 1) pulse width capture mode in this mode, the t imer/event counter can be utilised to measure the width of external pulses applied to the external timer pin. t o operate in this mode, the operating mode select bit pair , tm1/ tm0, in the t imer control register must be set to the correct value as shown. bit7 bit6 1 1 control register operating mode select bits for the pulse w idth measurement mode in this mode the internal clock, f sys is used as the internal clock for the 8-bit t imer/event counter . however, the clock s ource is further divided by a pres caler, the value of w hich is determined by the pre scaler ra te se lect bi ts t ps c 2~tps c 0, wh ich a re bi t s 2~0 of t he t imer con trol re gister . after other bits in the timer control register have been setup, the enable bit ton, which is bit 4 of the t imer control register , can be set high to enable the t imer/event counter , however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit te, which is bit 3 of the t imer control register , is low , once a high to low transition has been received on the external timer pin, the t imer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automatically reset to zero and the t imer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. as before, the enable bit will be automatically reset to zero and the t imer/event counter will stop counting. it is important to note that in the pulse width capture mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the t imer/event counter , which can now be read by the program, therefore represents t he l ength o f t he p ulse r eceived o n t he t mr p in. as t he e nable b it h as n ow b een r eset, any further t ransitions o n t he e xternal t imer p in wi ll b e i gnored. t he t imer c annot b egin f urther p ulse width capture until the enable bit is set high again by the program. in this way , single shot pulse measurements can be easily made. it should be noted that in this mode the t imer/event counter is controlled by logical transitions on the external timer pin and not by the logic level. w hen the t imer/event counter is full and overfows, an interrupt signal is generated and the t imer/event counter will reload the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the t imer/ event counter interrupt enable bit in the corresponding interrupt control register is reset to zero. as the external pin is shared with an i/o pin, to ensure that the pin is confgured to operate as a pulse width capture pin, two things have to happen. the frst is to ensure that the operating mode select bits in the timer control register place the t imer/event counter in the pulse width capture mode , the second is to ensure that the port control register confgures the pin as an input.
rev. 0.00 ? 0 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 ?1 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators
? ? ? ? ? ? ? ? pulse width capture mode timing chart (te= 0) programmable frequency divider C pfd the programmable frequency divider provides a means of producing a variable frequency output suitable for applications requiring a precise frequency generator. the pfd output is pin-shared with the i/o pin p a5. the pfd function is enabled via pfden bit in misc register, however, if not enabled, the pin can operate as a normal i/o pin. the output frequency is controlled by loading the required values into the timer registers and prescaler registers to give the required division ratio. the timer will begin to count-up from this preload re gister va lue unt il ful l, a t whi ch poi nt a n ove rfow si gnal i s generated, c ausing t he pfd output to change state. the timer will then be automatically reloaded with the preload register value and continue counting-up.

pfd output control misc register bit 7 6 5 4 3 2 1 0 na ? e ode3 ode ? ode1 ode0 pfden r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ode3 : pb3 open drain control 0: disable 1: enable bit ode2 : pb2 open drain control 0: disable 1: enable bit 5 ode1 : pb 1 open drain control 0: disable 1: enable bit 4 ode0 : pb 0 open drain control 0: disable 1: enable bit 3 ~ 1 unimplemented, read as 0 bit 0 pfden : pfd function control 0: disable 1: enable
rev. 0.00 ?0 ?e?te??e? ??? ?01? rev. 0.00 ? 1 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators prescaler bits tpsc0~tpsc2 of the tmrc register can be used to defne the pre-scaling stages of the internal clock sources of the t imer/event counter . the t imer/event counter overfow signal can be used to generate signals for the pfd and t imer interrupt. i/o interfacing the t imer/event counter , when confgured to run in the event counter or pulse width measurement mode, require s the use of the external pin for correct operation. as this pin is a shared pin it must be confgured correctly to ensure it is setup for use as a t imer/event counter input and not as a normal i/o pin. this is implemented by ensuring that the mode select bits in the t imer/event counter control register, se lect ei ther t he eve nt count er or pulse wi dth m easurement m ode. addi tionally the port control register must be set high to ensure that the pin is setup as an input. any pull-high resistor on this pin will remain valid even if the pin is used as a t imer/event counter input. timer/event counter pin internal filter the external t imer/event counter pin is connected to an internal flter to reduce the possibility of unwanted event counting events or inaccurate pulse width measurements due to adverse noise or spikes on the exte rnal t imer/event counter input signal. as this internal flter circuit will consume a limited amount of power , a confguration option is provided to switch of f the flter function, an option which m ay be be nefcial i n powe r se nsitive a pplications, but i n whi ch t he i ntegrity of t he input signal is high. care must be taken when using the flter on/of f confguration option as it will be applied not only to the external t imer/event counter pin but also to the external interrupt input pins. individual timer/event counter or external interrupt pins cannot be selected to have a flter on/of f function. programming considerations when c onfigured t o run i n t he t imer m ode, t he i nternal syst em c lock i s use d a s t he t imer c lock source and is therefore synchronised with the overall operation of the microcontroller . in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector . for the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when t he t imer/event c ounter i s r ead, o r i f d ata i s wr itten t o t he p reload r egister, t he c lock i s inhibited to avoid errors, however as this may result in a counting error , this should be taken into account by the programmer. care must be taken to ensure that the timer is properly initialised before using it f or the fr st t ime. t he a ssociated t imer e nable b it i n t he i nterrupt c ontrol r egister m ust b e properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bit in timer control register must also be correctly set t o e nsure t he t imer is p roperly c onfgured f or t he r equired a pplication. i t i s a lso i mportant t o ensure that an init ial value is frst loaded into the timer register before the timer is switched on; this is because after power -on the initial values of the timer register s are unknown. after the timer has been initi alised the timer can be turned on and of f by controlling the enable bit in the timer control register. note that setting the timer enable bit high to turn the timer on, should only be executed after
rev. 0.00 ?? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 ?3 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators the timer mode bit s have been properly setup. setting the timer enable bit high together with a mode bit modifcation, may lead to improper timer operation if executed as a single timer control register byte write instruction. when the t imer/event counter overfows, its corresponding interrupt request fag in the interrupt control r egister wi ll b e se t. i f t he t imer i nterrupt i s e nabled t his wi ll i n t urn g enerate a n i nterrupt signal. however irrespective of whether the interrupts are enabled or not, a t imer/event counter overflow will also generate a wake-up signal if the device is in a power -down condition. this situation may occur if the t imer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the t imer/event counter will continue to count these external events and if an overfow occurs the device will be woken up from its power -down condition. t o prevent such a wake-up from occurring, the timer interru pt request fag should frst be set high before issuing the halt instruction to enter the power down mode. timer program example this program example shows how the t imer/event counter register is setup, along with how the interrupt is enabled and managed. note how the t imer/event counter is turned on, by setting bit 4 of the t imer control register . the t imer/event counter can be turned of f in a similar way by clearing the same bit. this example program sets the t imer/event counter to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; external interrupt vector org 0ch ; timer/event counter interrupt vector jmp tmrint ; jump here when the timer/event counter overfows : org 20h ; main program ; internal timer/event counter interrupt routine : tmrint: ; timer/event counter main program placed here : reti: : begin: ; setup timer registers mov a,09bh ; setup timer preload value mov tmr,a mov a,081h ; setup timer control register mov tmrc,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,009h ; enable master interrupt and timer interrupt mov intc0,a set tmrc.4 ; start timer/event counter - note mode bits must be previously setup
rev. 0.00 ?? ?e?te??e? ??? ?01? rev. 0.00 ? 3 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators ldo function the device contain s a low power voltage regulator implemented in cmos technology. using cmos technology ensures low voltage drop and low quiescent current. there are two fxed output voltages of 2.4v and 3.3v , which can be controlled by a specifc register . the internal ldo output combined with various options by register can provide a fxed voltage for the op a reference voltage, and as a fxed power supply for external device. ldoc register bit 7 6 5 4 3 2 1 0 na ? e r ? el vloe ren1 vre ? v ? el ldoen r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~ 6 unimplemented, read as 0 bit 5 rsel : select resistor for r total 0: total 500 k 1: total 200 k bit 4 vloe : ldo output voltage control bit 0: disable 1: enable if the vloe and ldoen are set to 1, the ldo will output 2.4v or 3.3v to pin and disable i/o function. bit 3 ren1 : bias voltage divided resistor control bit 0: disable 1: enable if the ren1 is set to 1, that will turn on the resistor dc path, which will generate bias voltage for opas. bit 2 vres : divided resistor voltage supply selection bit 0: vdd 1: vldo bit 1 vsel : ldo output voltage selection bit 0: 2.4v 1: 3.3v bit 0 ldoen : ldo control bit 0: disable 1: enable note: 1. the total resistance of the divided resistor , 500 k or 200 k , can be selected by the rsel fag. 2. t o disable the ldo function will turn of f the buf1 as well, no matter the ldo output voltage control bit, vloe, is enabled or not. 3 . if the ldo is disabled, ldoen=0, then the sw4 will be turned to vdd, no matter vres fag is 1 or not. the following block diagram illustrates the functional structure for ldo and divided resister.
rev. 0.00 ? 4 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 ?5 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators ldo (?.4v/3.3v) v?el vdd ldoen out ren1 vldox vh1 (0.9*vldox) vh0 ([0.5+1/1?]*vldox) vm (0.5*vldox) vl0 ([0.5-1/1?]*vldox) vl1 (0.1*vldox) vloe vloe buf1 ?w4 ?w5 ldo (?.4v/3.3v)? ?ust ?e connected f?o? the ?in r total = 500k o? ?00k vcap/pc4 operational amplifers there are two fully integrated operational amplifers in the device, op a1 and op a2. these op as can be use d for si gnal am plification ac cording t o spe cific use r requi rements. t he op as ca n be disabled o r enabled e ntirely u nder so ftware c ontrol u sing i nternal r egisters. w ith sp ecifc c ontrol registers, some opa related applications can be more fexible and easie r to be implemented, such as unit gain buf fer, non-inverting amplifer , inverting amplifer and various kinds of flters, etc. in addition, the device provides the calibration function to adjust the opa offset. operational amplifer registers the internal o perational a mplifiers are fully under the control of internal regis ters, o pa1c0, opa1c1, op a2c0, op a2c1 and op a2c2. these registers control enable/disable function, input path selection, gain control, polarity and calibration function. opa1c0 register bit 7 6 5 4 3 2 1 0 na ? e a1op a1ofm a1r ? a1of4 a1of3 a1of ? a1of1 a1of0 r/w r r/w r/w r r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 : operational amplifer output; positive logic. this bit is read only. bit 6 : operational amplifer mode or input offset voltage cancellation mode 0: operational amplifer mode 1: input offset voltage cancellation mode bit 5 : operational amplifer input offset voltage cancellation reference selection bit 0: select a1n as the reference input 1: select a1p as the reference input bit 4 ~0 : operational amplifer input offset voltage cancellation control bits
rev. 0.00 ?4 ?e?te??e? ??? ?01? rev. 0.00 ? 5 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators opa1c 1 register bit 7 6 5 4 3 2 1 0 na ? e a1o ? cin a1o ? n a1p ? el1 a1p ? el0 a1p ? a1n ? a1oen a1en r/w r/w r/w r/w r r/w r/w r/w r/w por 0 0 0 0 1 1 0 0 bit 7 : opa1 output to comparator input control bit 0: disable 1: enable bit 6 : opa1 output to opa1 inverting input control bit 0: disable 1: enable bit 5 ~4 : opa1 non-inverting input selection bit 0 0 : no connection 0 1: from 0.9v ldo 10 : from vm 1 1: from 0.1v ldo bit 3 : opa1 positive input switch on/off bit 0 : off 1: on bit 2 : opa1 negative input switch on/off bit 0 : off 1: on bit 1 : opa1 output enable or disable control bit 0: disable 1: enable bit 0 : opa1 enable or disable control bit 0: disable 1: enable opa 2c0 register bit 7 6 5 4 3 2 1 0 na ? e a ? op a ? ofm a ? r ? a ? of4 a ? of3 a ? of ? a ? of1 a ? of0 r/w r r/w r/w r r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 : operational amplifer output; positive logic. this bit is read only. bit 6 : operational amplifer mode or input offset voltage cancellation mode 0: operational amplifer mode 1: input offset voltage cancellation mode bit 5 : operational amplifer input offset voltage cancellation reference selection bit 0: select a 2 n as the reference input 1: select a 2 p as the reference input bit 4 ~0 : operational amplifer input offset voltage cancellation control bits
rev. 0.00 ?? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 ?7 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators opa 2c1 register bit 7 6 5 4 3 2 1 0 na ? e a ? o ? cin a ? o ? n a ? p ? el1 a ? p ? el0 a ? p ? a ? n ? a ? oen a ? en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 1 0 0 bit 7 : opa 2 output to comparator input control bit 0: disable 1: enable bit 6 : opa 2 output to opa 2 inverting input control bit 0: disable 1: enable bit 5 ~4 : opa 2 non-inverting input selection bit 0 0 : no connection 0 1: from 0.9v ldo 10 : from vm 1 1: from 0.1v ldo bit 3 : opa2 positive input switch on/off bit 0 : off 1: on bit 2 : opa2 negative input switch on/off bit 0: off 1: on bit 1 : opa 2 output enable or disable control bit 0: disable 1: enable bit 0 : opa 2 enable or disable control bit 0: disable 1: enable opa 2c2 register bit 7 6 5 4 3 2 1 0 na ? e a 1 o ? a ? n a1o ? a ? p pgaen pga ? pga1 pga0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 : opa1 output to opa2 inverting input control bit 0: disable 1: enable bit 6 : opa1 output to opa2 non-inverting input control bit 0: disable 1: enable bit 5 ~4 unimplemented, read as 0 bit 3 : opa2 pga gain enable control bits 0 : off 1: on bit 2 ~0 : opa2 gain control bits 000: 1 001: 8 010: 16 011: 24 100: 32 101: 40 110: 48 111: 56
rev. 0.00 ?? ?e?te??e? ??? ?01? rev. 0.00 ? 7 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators operational amplifer operation the advantages of multiple switches and input path options, various reference voltage selection, up to 8 kinds of inter nal software gain control, of fset reference voltage calibration function and power down control for low power consumption enhance the fexibility of these two op as to suit a wide range of application possibilities. the following block diagram illustr ates the main functional blocks of the op as and comparator in this device. a? a?n a?e a1 a1n a1p vm mux 10k 5?0k a1n? a1o?n a?o?n r1 r? a1p?el[1:0] a1op c1 c? a1p? a1oen a?op a?oen a1e a1o?a?n a1o?a?p a?p a?n? pgaen pgaen a?p? a1o?cin a?o?cin c?outen c1outen cinto c1inten c?inten c1n?el c?p?el c1out c?out c1n c?p cnp cnp?el cmp1op cmp?op edge ?elect cmpe?[1:0] cmpint cinto mux vh mux vl vm mux a?p?el[1:0] operational amplifer functions the o pas are connected together internally in a s pecific w ay and the output of o pas can als o be connected t o t he i nternal c omparators a s sh own i n t he b lock d iagram. e ach o f t he op as h as i ts o wn control register, with the name op a1c0, op a1c1, op a2c0, op a2c1 and op a2c2 which are used to control the enable/disable function, the calibration procedure and the programmable gain function of opa2 . each of the internal opas allows for a common mode adjustment method of its input offset voltage. the calibration steps are as following: ? set a1ofm=1 to setup the offset cancellation mode, here s3c is closed. ? set a1rs to select which input pin is to be used as the reference voltage - s1c or s2c is closed ? adjust a1of0~a1of4 until the output status changes ? set a1ofm = 0 to restore the normal opa mode ? repeat the same procedure from steps 1 to 4 for opa2

rev. 0.00 ? 8 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 ?9 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators opa1 switch control the follow ing diagram and table illus trate the o pa1 s witch control s etting and the corres ponding connections. note that some switch control selections will force some switches to be controlled by hardware automatically. for example: ? the s7c is closed when a1o2cin= 1 and the s7c is opened when a1o2cin = 0. ? the a1ps= 1 will force a1psel1, 0 = (00), i.e. s10c, s9c, s8c will be opened. ? when the a1en= 0, s6c switch are opened by hardware, then the related i/o pins can be used as the other functions. opa1 switch control : the following table illustrates the relationship between op a1 control register settings and the switches: opa1 control bits in opa1c0, opa1c1 switch description results a1ps a1ns a1ofm a1rs a1psel1 a1psel0 a1o2n s4c s5c s6c s8c~ s10c opa1 connections 1 1 1 0 00 0 on on off off cali ?? at ion ? ode ? a 1n 1 1 1 1 00 0 on on off off cali ?? ation ? ode ? a1p 1 1 0 00 0 on on off off in ? ut = a1n ? a1p 0 1 0 01 0 off on off ? 10c on in ? ut = a1n ? vh1 0 1 0 10 0 off on off ? 9c on in ? ut = a1n ? vm 0 1 0 11 0 off on off ? 8c on in ? ut = a1n ? vl1 1 1 0 00 1 on on on off in ? ut = a1n ? a1p ? connect a1n ? a1e 1 0 0 00 1 on off on off in ? ut = a1p ? opa1 as ? uffe ? 0 1 0 01 0 off on off ? 10c on in ? ut = a1n ? vh1 0 1 0 10 0 off on off ? 9c on in ? ut = a1n ? vm 0 1 0 11 0 off on off ? 8c on in ? ut = a1n ? vl1 note: 1. s7c is closed when a1o2cin=1, s7c is opened when a1o2cin =0. 2 . when a1ofm=1, s3c, s4c, s5c are closed, s6c, s8c~s10c are always opened. opa 1 a 1 e a 1 n a 1 p a 1 op a 1 oe n cmp 1 cmp 2 v l 1 v m v h 1 opa 2 a 1 o 2 c i n a 1 o 2 n a 1 o 2 a 2 n a 1 n s a 1 p s s 4 c s 5 c s 6 c s 7 c s 8 c s 9 c s 1 0 c s3 c s 2 c s 1 c a 1 r s a 1 o f m s 1 c s 2 c 0 0 o n o n 0 1 o f f o n 1 0 o n o n a 1 o 2 a 2 p a 1 p s = 1 wi l l f o r c e a 1 p s e l 1 , 0 = (0 0 ) , i . e . s 1 0 c , s9 c , s 8 c wi l l b e o p e n e d .
rev. 0.00 ?8 ?e?te??e? ??? ?01? rev. 0.00 ? 9 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators opa1 & i/o status description: the following table illustrates the opa1 & i/o settings. a1en a1ns a1ps description 0 pa ? and pa3 and pa4 a ? e i/os 1 0 0 pa ? and pa3 a ? e i/os ? pa4 is opa1 a1e out ? ut 1 0 1 pa3 is i/o. pa ? is opa1 a1p in ? ut ? pa4 is opa1 a1e out ? ut 1 1 0 pa ? is i/o. pa3 is opa1 a1n in ? ut ? pa4 is opa1 a1e out ? ut 1 1 1 pa ? is opa1 a1p in ? ut and pa3 is opa1 a1n in ? ut ? pa4 is opa1 a1e out ? ut opa2 switch control the follow ing diagram and table illus trate the o pa2 s witch control s etting and the corres ponding connections. note that some switch control selections will force some switches to be controlled by hardware automatically. for example: ? the pgaen=1 will force s6d, s7d to close and the pgaen=0 will force s6d, s7d to open. ? when the a2en=0, these switches, s6d, s7d and s9d, are opened by hardware, then the related i/o pins can be used as the other functions. opa 2 a 2 e a2 n a 2 p s 1 d a 2 op a 2 oe n cmp 1 cmp 2 v l 1 v m v h 1 a 2 o 2 c i n a 2 o 2 n a 1 o 2 a 2 n o p a 1 1 0 k s 2 d 5 6 0 k s 6 d s 7 d s 8 d s 9 d s 1 0 d s 1 1 d a2 n s a 2 p s s 1 2 d s 1 3 d s 1 4 d a 2 r s a 2 o f m s1 d s2 d s3 d 0 0 o n o n o f f 0 1 o f f o n o n 1 0 o n o n o f f 1 1 o n o f f o n s 3 d s 4 d s 5 d a 1 o 2 a 2 p s wi t c h p r i o r i t y : s 4 d > s1 1 d > ( s 1 2 d , s 1 3 d , s 1 4 d ) ; i f a 2 p s = 1 , s 1 1 d ~ s 1 4 d wi l l b e o p e n e d b y h a r d wa r e . s wi t c h p r i o r i t y : s 5 d > s8 d ; i f a 2 n s = 1 , s 8 d wi l l b e o p e n e d b y h a r d wa r e .
rev. 0.00 70 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 71 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators opa2 switch control: the following table illustrates the relationship between op a2 control register settings and the switches: opa2 control bits in opa2c0, opa2c1, opa2c2 switch description results a2ps a2ns a2ofm a2rs a2psel1,0 a1o2a2p a1o2a2n pgaen a2o2n s4d s5d s6/7d s8d s9d s11d s12d~s14d opa2 connections 1 0 1 1 00 0 0 0 0 on on off off off off off cali ?? ation ? ode ? in ? ut = a ? p 1 1 1 0 00 0 0 0 0 on on off off off off off cali ?? ation ? ode ? in ? ut = a ? n 1 1 0 00 0 0 0 0 on on off off off off off no ?? al ? ode ? in ? ut = a ? n ? a ? p 0 1 0 01 0 0 0 0 off on off off off off ? 1 ? d on in ? ut = a ? n ? vh1 0 1 0 10 0 0 0 0 off on off off off off ? 13d on in ? ut = a ? n ? vm 0 1 0 11 0 0 0 0 off on off off off off ? 14d on in ? ut = a ? n ? vl1 0 1 0 00 1 0 0 0 off on off off off on off in ? ut = a ? n ? a1e 1 0 0 00 0 1 0 0 on off off on off off off in ? ut = a1e ? a ? p 1 1 0 00 0 0 1 0 on on on off off off off in ? ut = a ? n ? a ? p 1 0 0 00 0 0 1 0 on off on off off off off in ? ut = a ? n ? a ? p 1 0 0 00 0 0 0 1 on off off off on off off in ? ut = a ? p ? opa ? as ? uffe ? 0 0 0 01 0 0 0 1 off off off off off off ? 1 ? d on in ? ut = vh1 ? opa ? as ? uffe ? 0 0 0 10 0 0 0 1 off off off off off off ? 13d on in ? ut = vm ? opa ? as ? uffe ? 0 0 0 11 0 0 0 1 off off off off off off ? 14d on in ? ut = vl1 ? opa ? as ? uffe ? opa2 & i/o status description: the following table illustrates the opa2 & i/o settings. a2en pgaen a2ns a2ps description 0 pa5 and pa ? and pa7 a ? e i/os 1 0 0 0 pa5 and pa ? a ? e i/os. pa7 is opa ? a ? e out ? ut 1 0 0 1 pa ? is i/o. pa5 is opa ? a ? p in ? ut ? pa7 is opa ? a ? e out ? ut 1 0 1 0 pa5 is i/o. pa ? is opa ? a ? n in ? ut ? pa7 is opa ? a ? e out ? ut 1 0 1 1 pa5 is opa ? a ? p in ? ut and pa ? is opa ? a ? n in ? ut ? pa7 is opa ? a ? e out ? ut 1 1 0 0 pa5 is i/o. pa ? is opa ? a ? n in ? ut ? pa7 is opa ? a ? e out ? ut 1 1 0 1 pa5 is opa ? a ? p in ? ut and pa ? is opa ? a ? n in ? ut ? pa7 is opa ? a ? e out ? ut 1 1 1 0 pa5 is i/o. pa6 is opa2 a2n input and bypass r1 (10k), pa7 is opa2 a2e out ? ut 1 1 1 1 pa5 is opa2 a2p input and pa6 is opa2 a2n input and bypass r1 (10k), pa7 is opa ? a ? e out ? ut
rev. 0.00 70 ?e?te??e? ??? ?01? rev. 0.00 71 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators comparator two anal og comparators are contai ned within this device. these functions of fer fexibility via their register controlled features such as power -down, interrupt etc. in sharing their pins with normal i/ o pins, the comparators do not waste precious i/o pins if there functions are otherwise unused. in addition, the device provides the calibration function to adjust the comparator offset. comparator operation the de vice c ontain s two c omparator fu nctions whi ch a re use d t o c ompare t wo a nalog v oltages and provide an output based on their dif ference. full control over the two internal comparators is provided via control registers, cmp1c0, cmp1c1, cmp2c0 and cmp2c1. the comparator output is recorded via a bit in their respective control register , but can also be transferred out onto a shared i/o pin or to generate an interrupt trigger with edge control function. additional comparator functions include the power down control. comparator registers the inter nal dual comparators are fully under the control of internal registers, cmp1c0, cmp1c1, cmp2c0 and cmp2c1. these registers control enable/disable function, input path selection, interrupt edge control and input offset voltage calibration function. cmp1c0 register bit 7 6 5 4 3 2 1 0 na ? e cmp1op c1ofm c1r ? c1of4 c1of3 c1of ? c1of1 c1of0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 : comparator output; positive logic. this bit is read only. bit 6 : comparator mode or input offset voltage cancellation mode 0: comparator mode 1: input offset voltage cancellation mode when the c1ofm=1, comparator inputs are always from i/o pins. i.e. the cnpsel and c1nsel will be forced to 1. that means disconnect the input from op as output. bit 5 : comparator input offset voltage cancellation reference selection bit 0: select c1n as the reference input 1: select cnp as the reference input bit 4~0 : comparator input offset voltage cancellation control bits cmp1c1 register bit 7 6 5 4 3 2 1 0 na ? e cnp ? el c1inten c1outen c1n ? el cmp1en r/w r/w r/w r/w r/w r/w por 1 0 0 1 0 bit 7 : comparator non-inverting input control bit 0: from opa output 1: from cnp pin bit 6 ~4 unimplemented, read as 0 bit 3 : comparator 1 interrupt control bit 0: disable 1: enable
rev. 0.00 7 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 73 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators bit 2 c1outen : comparator 1 output pin control bit 0: disable 1: enable bit 1 c1nsel : comparator 1 inverting input control bit 0: from vh0 1: from c1n pin bit 0 cmp1en : comparator 1 enable or disable control bit 0: disable 1: enable cmp2c0 register bit 7 6 5 4 3 2 1 0 na ? e cmp ? op c ? ofm c ? r ? c ? of4 c ? of3 c ? of ? c ? of1 c ? of0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 1 0 0 0 0 bit 7 cmp2op : comparator output; positive logic. this bit is read only. bit 6 c2ofm : comparator mode or input offset voltage cancellation mode 0: comparator mode 1: input offset voltage cancellation mode when the c 2 ofm=1, comparator inputs are always from i/o pins. i.e. the cnpsel and c1nsel will be forced to 1. that means disconnect the input from op as output. bit 5 c2rs : comparator input offset voltage cancellation reference selection bit 0: select c 2p as the reference input 1: select cnp as the reference input bit 4~0 c2of4~c2of0 : comparator input offset voltage cancellation control bits cmp2c1 register bit 7 6 5 4 3 2 1 0 na ? e cmpe ? 1 cmpe ? 0 c ? inten c ? outen c ? p ? el cmp ? en r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 1 0 bit 7 ~6 cmpes1, cmpes0 : interrupt edge control bits 00: disable 01: rising edge trigger 10: falling edge trigger 11: dual edge trigger bit 5~4 unimplemented, read as 0 bit 3 c2inten : comparator 2 interrupt control bit 0: disable 1: enable bit 2 c2outen : comparator 2 output pin control bit 0: disable 1: enable bit 1 c2psel : comparator 2 non-inverting input control bit 0: from v l0 1: from c 2p pin bit 0 cmp2en : comparator 2 enable or disable control bit 0: disable 1: enable
rev. 0.00 7? ?e?te??e? ??? ?01? rev. 0.00 73 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators comparator functions theses two comparators can operate together with the op as or standalone as shown in the main functional blocks of the opas and comparators. each of the intern al comparators allows for a common mode adjustme nt method of its input of fset voltage. the calibration steps are as following: ? set c1ofm=1 to setup the offset cancellation mode, here s3a is closed. ? set c1rs to select which input pin is to be used as the reference voltage - s1a or s2a is closed. ? adjust c1of0~c1of4 until the output status changes. ? set c1ofm = 0 to restore the normal comparator mode. ? repeat the same procedure from steps 1 to 4 for comparator 2.

??

the fol lowing di agram a nd t able i llustrate t he c omparators swi tch c ontrol se tting a nd t he corresponding connections. note that some switch control selections will force some switches to be controlled by hardware automatically. for example: ? when the cmp1 in calibration mode, i.e. c1ofm =1, then the sw1, sw3 will be forced to close. the cnpsel and c1nsel bits will be set 1 by hardware, and these two bits will be read out as 1. after the offset voltage calibration, the cnpsel and c1nsel will be back to its original value. ? when the cmp2 in calibration mode, i.e. c2ofm =1, then the sw1, sw2 will be forced to close. ? the cnpsel and c2psel bits will be set 1 by hardware, and these two bits will be read out as 1. after the offset voltage calibration, the cnpsel and c2psel will be back to its original value. ? if the cnpsel=1, the a1o2cin and a2o2cin will be forced to 0, i.e. if the swi is closed, and that will force s7c and s10d to open. ? if the cnpsel=0 and the a1o2cin=1, the a2o2cin will be forced to 0, i.e. if the s7c is closed, and that will force s10d to open.
rev. 0.00 74 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 75 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators cmp1 & i/o status description: the following table illustrates the cmp1 & i/o settings. cmp1en c1outen cnpsel c1nsel description 0 pc5 and pa0 and pa1 a ? e i/os 1 0 0 0 cnp is f ? o ? opa1 o ? opa ? out ? ut ? c1n is f ? o ? vh0 in ? ut ? pa1 is i/o 1 0 0 1 cnp is f ? o ? opa1 o ? opa ? out ? ut ? c1n is f ? o ? pc5 in ? ut ? pa1 is i/o 1 0 1 0 cnp is f ? o ? pa0 in ? ut ? c1n is f ? o ? vh0 in ? ut ? pa1 is i/o 1 0 1 1 cnp is f ? o ? pa0 in ? ut ? c1n is f ? o ? pc5 in ? ut ? pa1 is i/o 1 1 0 0 cnp is f ? o ? opa1 o ? opa ? out ? ut ? c1n is f ? o ? vh0 in ? ut ? pa1 is co ?? a ? ato ? out ? ut 1 1 0 1 cnp is f ? o ? opa1 o ? opa ? out ? ut ? c1n is f ? o ? pc5 in ? ut ? pa1 is co ?? a ? ato ? out ? ut 1 1 1 0 cnp is f ? o ? pa0 in ? ut ? c1n is f ? o ? vh0 in ? ut ? pa1 is co ?? a ? ato ? out ? ut 1 1 1 1 cnp is f ? o ? pa0 in ? ut ? c1n is f ? o ? pc5 in ? ut ? pa1 is co ?? a ? ato ? out ? ut cmp2 & i/o status description: the following table illustrates the cmp2 & i/o settings. cmp2en c2outen cnpsel c2psel description 0 pc ? and pa0 and pa ? a ? e i/os 1 0 0 0 cnp is f ? o ? opa1 o ? opa ? out ? ut ? c ? p is f ? o ? vl0 in ? ut ? pa ? is i/o 1 0 0 1 cnp is f ? o ? opa1 o ? opa ? out ? ut ? c ? p is f ? o ? pc ? in ? ut ? pa ? is i/o 1 0 1 0 cnp is f ? o ? pa0 in ? ut ? c ? p is f ? o ? vl0 in ? ut ? pa ? is i/o 1 0 1 1 cnp is f ? o ? pa0 in ? ut ? c ? p is f ? o ? pc ? in ? ut ? pa ? is i/o 1 1 0 0 cnp is f ? o ? opa1 o ? opa ? out ? ut ? c ? p is f ? o ? vl0 in ? ut ? pa ? is co ?? a ? ato ? out ? ut 1 1 0 1 cnp is f ? o ? opa1 o ? opa ? out ? ut ? c ? p is f ? o ? pc ? in ? ut ? pa ? is co ?? a ? ato ? out ? ut 1 1 1 0 cnp is f ? o ? pa0 in ? ut ? c ? p is f ? o ? vl0 in ? ut ? pa ? is co ?? a ? ato ? out ? ut 1 1 1 1 cnp is f ? o ? pa0 in ? ut ? c ? p is f ? o ? pc ? in ? ut ? pa ? is co ?? a ? ato ? out ? ut
rev. 0.00 74 ?e?te??e? ??? ?01? rev. 0.00 75 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators comparators switch control: the following table illustrates the relationship between comparators control register settings and the switches: cmp1,cmp2 control bits switch description results cnpsel c2psel c1nsel c1ofm c1rs sw1 sw2 sw3 s1a s2a s3a s7c s10d connections 1 (fo ? ced to 1) 1 (fo ? ced to 1) 1 1 on cnp on c1n on off on off off in ? ut co ?? on ? ode = cnp 1 (fo ? ced to 1) 1 (fo ? ced to 1) 1 0 on cnp on c1n off on on off off in ? ut co ?? on ? ode = c1n 1 0 1 0 on c1n on on off off off in ? ut = cnp ? c1n 1 0 0 0 on vh on on off off off in ? ut = cnp ? vh1 0 0 1 0 off c1n on on off on off in ? ut = a1e ? c1n 0 0 1 0 off c1n on on off off on in ? ut = a ? e ? c1n interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such a s a t imer/event count er re quires m icrocontroller a ttention, t heir c orresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions the external interrupts are generated by the action of the external int0~int1 pins, while the internal interrupts are generated by various internal functions such as the comparator, timer/event counter etc. interrupt registers overall i nterrupt c ontrol, whi ch ba sically m eans i nterrupt e nabling a nd re quest fl ag se tting, i s controlled by the intc0, in tc1, m fic0 and m fic1 regis ters, w hich are located in the d ata memory. by controlling the appropriate enable bits in these registers each individual interrupt can be enable d or disabled. also when an interrupt occurs, the corresponding request fag will be set by the microcontroller. the global enable fag if cleared to zero will disable all interrupts. interrupt operation a t imer/event counter overfow, t ime base 0/1, the external interrupt line being triggered, a comparator output, an eeprom w rite or read cycle ends will all generate an interrupt request by setting their corresponding r equest f lag, i f t heir a ppropriate i nterrupt e nable b it i s se t. w hen t his h appens, t he program counter , which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagram with their order of priority.
rev. 0.00 7 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 77 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however , if other interrupt requests occur during this interval, although the inter rupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. interrupt priority interrupts, occurri ng in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. interrupt source priority vector exte ? nal inte ?? u ? t 0 1 04h exte ? nal inte ?? u ? t 1 ? 08h ti ? e ? /event counter overfow 3 0ch multi-function inte ?? u ? t 4 18h the t ime base interrupt s , comparator interrupt and eeprom interrupt all share the same interrupt vector which is 18h. each of these interrupts has their own individual interrupt fag but also share the sa me mff i nterrupt fa g. the mff fa g wi ll be c leared by ha rdware onc e t he mul ti-function interrupt is serviced, however the individual interrupts that have triggered the multi-function interrupt need to be cleared by the application program. intc0 register bit 7 6 5 4 3 2 1 0 na ? e tf eif1 eif0 eti eei1 eei0 emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 : t imer/event counter interrupt request fag 0: inactive 1: active bit 5 : external interrupt 1 request fag 0: inactive 1: active bit 4 : external interrupt 0 request fag 0: inactive 1: active bit 3 : t imer/event counter interrupt enable 0: disable 1: enable bit 2 : external interrupt 1 enable 0: disable 1: enable bit 1 : external interrupt 0 enable 0: disable 1: enable bit 0 : master interrupt global enable 0: global disable 1: global enable
rev. 0.00 7? ?e?te??e? ??? ?01? rev. 0.00 77 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators intc1 register bit 7 6 5 4 3 2 1 0 na ? e mff emfi r/w r/w r/w por 0 0 bit 7 unimplemented, read as 0 bit 6 mff : multi-function interrupt request fag 0: inactive 1: active bit 5 ~3 unimplemented, read as 0 bit 2 emfi : multi-function interrupt enable 0: disable 1: enable bit 1~0 unimplemented, read as 0 mfic0 register bit 7 6 5 4 3 2 1 0 na ? e tb1f tb0f tb1e tb0e r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 tb1f : t ime base 1 interrupt request fag 0: inactive 1: active bit 5 tb0f : t ime base 0 interrupt request fag 0: inactive 1: active bit 4~3 unimplemented, read as 0 bit 2 tb1e : t ime base 1 interrupt enable 0: disable 1: enable bit 1 tb0e : t ime base 0 interrupt enable 0: disable 1: enable bit 0 unimplemented, read as 0
rev. 0.00 78 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 79 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators mfic1 register bit 7 6 5 4 3 2 1 0 na ? e e ? f cf e ? i eci r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~6 unimplemented, read as 0 bit 5 e2f : eeprom interrupt request fag 0: inactive 1: active bit 4 cf : comparator interrupt request fag 0: inactive 1: active bit 3~2 unimplemented, read as 0 bit 1 e2i : eeprom interrupt enable 0: disable 1: enable bit 0 eci : comparator interrupt enable 0: disable 1: enable external interrupt the external interrupts are controlled by signal transitions on the pins int0~ int1 . an external interrupt request will take place when the external interrupt request fags, eif0~eif1, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, eei0~eei1, must first be set. a dditionally the correct interrupt edge type mus t be s elected us ing the in tedge regis ter to enable the externa l interrupt functio n and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subrout ine c all t o t he e xternal i nterrupt ve ctor, wi ll t ake pl ace. w hen t he i nterrupt i s se rviced, the external interr upt request fags, eif0~eif1, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the intedge register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the intedge register can also be used to disable the external interrupt function.

rev. 0.00 78 ?e?te??e? ??? ?01? rev. 0.00 79 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators

? ? ? ? ? ?- ? ? ?? ? ? ? ?? ? ?? ? ?
?? ? ?? ? ?? ? ? ?? ? ?? ? ? ? ? ? ? interrupt structure the external interrupt pins are connected to an internal flter to reduce the possibility of unwanted external interrupts due to adverse noise or spikes on the external interrupt input signal. as this internal flter circuit will consume a limited amount of power , a confguration option is provided to switch of f the flter function, an option which may be benefcial in power sensitive applications, but in which the integrity of the input signal is high. care must be taken when using the flter on/of f confguration option as it will be applied not only to both the external interrupt pins but also to the timer/event counter external input pin. individual external interrupt or t imer/event counter pin cannot be selected to have a flter on/off function. intedge register bit 7 6 5 4 3 2 1 0 na ? e int1 ? 1 int1 ? 0 int0 ? 1 int0 ? 0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 int1s1, int1s0 : int1 edge select 00: disable 01: rising edge trigger 10: falling edge trigger 11: dual edge trigger bit 1 ~0 int0s1, int0s0 : int0 edge select 00: disable 01: rising edge trigger 10: falling edge trigger 11: dual edge trigger
rev. 0.00 80 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 81 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators timer/event counter interrupt for a t imer/event counter interrupt to occur , the global interrupt enable bit, em i, and the corresponding timer interrupt enable bit, eti, must first be set. an actual t imer/event counter interrupt will take place when the t imer/event counter request fag, tf , is set, asituation that will occur when the t imer/event counter overfows. when the interrupt is enabled, the stack is not full and a t imer/event counter overfow occurs, a subroutine call to the timer interrupt vector at location 0ch, wi ll t ake p lace. w hen t he i nterrupt i s se rviced, t he t imer i nterrupt request fa g, t f, wi ll b e automatically reset and the emi bit will be automatically cleared to disable other interrupts. time base interrupt the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the time bas e overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section.

? ? ? time base interrupt
rev. 0.00 80 ?e?te??e? ??? ?01? rev. 0.00 81 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators tbc register bit 7 6 5 4 3 2 1 0 na ? e tbon tbck tb11 tb10 tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 bit 7 tbon : tb0 and tb1 control bit 0: disable 1: enable bit 6 tbck : select f clock 0: f tbc 1: f /4 bit 5~4 tb11 ~ tb10 : select t ime base 1 t ime-out period 00: 4096/f 01: 8192/f 10: 16384/f 11: 32768/f bit 3 unimplemented, read as "0" bit 2~0 tb02 ~ tb00 : select t ime base 0 t ime-out period 000: 256/f 001: 512/f 010: 1024/f 011: 2048/f 100: 4096/f 101: 8192/f 110: 16384/f 111: 32768/f multi-function interrupt an additional interrupt known as the multi-function interrupt is provided. unlike the other interrupts, this interrupt has no independent source, but rather is formed from four other existing interrupt sources, namely the t ime base interrupts, comparator interrupt and eeprom interrupt. for a multi-function interrupt to occur , the global interrupt enable bit, emi, and the multi-function interrupt enable bit, emfi, must first be set. an actual multi-function interrupt will take place when the multi-function interrupt request flag, mff , is set. this will occur when either a t ime base overfow, a c omparator o utput interrupt o r an eep rom w rite or read cycle ends interrupt is generated. when the interrupt is enabled and the stack is not full, and either one of the interrupts contained within the multi-function interrupt occurs, a subroutine call to the multi-function interrupt vector at location 018h will take place. when the interrupt is serviced , the multi-function request fag, mff , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. howe ver, it m ust be no ted t hat t he re quest fa gs fro m t he or iginal sour ce of t he mul ti- function i nterrupt, na mely the t ime-base i nterrupt or a com parator out put interrupt, wi ll not be automatically reset and must be manually reset by the application program. comparator interrupt the comparator interrupt is contained within the multi-function interrupt. the comparator interrupt is controlled by the two internal comparators. a comparator interrupt request will take place when the comparator interrupt request flag, cf , is set, a situation that will occur when the comparator output changes state. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, the multi-function interrupt enable bit emfi and comparator
rev. 0.00 8 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 83 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators interrupt e nable bi t, e ci, m ust frst be set. w hen t he i nterrupt i s e nabled, t he st ack i s not ful l a nd the comparator input generates a comparator output transition, a subroutine call to the comparator interrupt vector , wil l take place. when the comparator int errupt is servi ced, the emi bit wil l be automatically clea red to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the cf fag will not be autom atically cleared, it has to be cleared by the application program. eeprom interrupt the eeprom interrupt, is contained within the multi-function interrupt. an eeprom interrupt request wi ll t ake p lace wh en t he e eprom i nterrupt r equest fa g, e 2f, i s se t, wh ich o ccurs wh en an eeprom w rite or read cycle ends. t o allow the program to branch to its respective interrupt vector a ddress, t he g lobal i nterrupt e nable b it, e mi, e eprom i nterrupt e nable b it, e2i , a nd the multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective multi-function interrupt vector, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the e2f fag will not be automatically cleared, it has to be cleared by the application program. interrupt wake-up function each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions o n t he e xternal i nterrupt p ins, a l ow p ower su pply v oltage o r c omparator i nput c hange may cause their respective interrupt fag to be set high and consequent ly generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function. programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register s until the corresponding interrupt is serviced or until the request fag is cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the contents of the status or other registers are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance.
rev. 0.00 8? ?e?te??e? ??? ?01? rev. 0.00 83 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators buzzer operating in a similar way to the programmable frequency divider , the buzzer function provides a means o f p roducing a v ariable f requency o utput, su itable f or a pplications su ch a s pi ezo-buzzer driving or ot her e xternal c ircuits t hat re quire a pre cise fre quency ge nerator. t he bz a nd bz pi ns form a complimentary pa ir, a nd a re pi n-shared wi th i/ o pi ns, p a6 a nd p a7. a bpct l re gister i s used to select from one of three buzzer options. the frst option is for both pins p a6 and p a7 to be used as normal i/os, the second option is for both pins to be confgured as bz and bz buzzer pins, the third option selects only the p a6 pin to be used as a bz buzzer pin with the p a7 pin retaining its normal i/o pin function. note that the bz pin is the inverse of the bz pin which together generates a differential output which can supply more power to connected interfaces such as buzzers. the buzzer is driven by the internal clock source, f tb , which then passes through a divider , the division ratio of which is selected by bpctl register to provide a range of buzzer frequencies from f tb /2 2 to f tb /2 9 . the clock source that generates f tb , which in turn controls the buzzer frequency , can originate from two dif ferent sources, the lirc oscillator or the system oscillator/4, the choice of which is determin ed by the f tb clock source option. note that the buzzer frequency is controlled by bpctl register, which select the source clock for the internal clock f tb .
? ?? ? buzzer function if the bpctl options have selected both pins p a6 and p a7 to function as a bz and bz complementary pair of buzzer outputs, then for correct buzzer operatio n it is essential that both pins must be set up a s outputs by set ting bi ts p ac6 a nd p ac7 of t he p ac port c ontrol re gister t o z ero. the pa6 data bit in the pa data register must also be set high to enable the buzzer outputs, if set low, both pins p a6 and p a7 will remain low . in this way the single bit p a6 of the p a register can be used as an on/of f control for both the bz and bz buzzer pin outputs. note that the p a7 data bit in the p a register has no control over the bz buzzer pin pa7. bpctl register bit 7 6 5 4 3 2 1 0 na ? e bc1 bc0 bz ? bz1 bz0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~ 5 unimplemented, read as 0 bit 4~3 : buzzer or i/o 00: pa7 is i/o, pa6 is i/o 01: pa7 is i/o, pa6 is bz 10: reserved 11: pa7 is bz , pa6 is bz bit 1 ~0 : buzzer output frequency selection 000 : f tb /2 2 00 1: f tb /2 3 0 10: f tb /2 4 0 11: f tb /2 5 100 : f tb /2 6 10 1: f tb /2 7 1 10: f tb /2 8 1 11: f tb /2 9
rev. 0.00 84 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 85 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators pac register pac6 pac register pac7 pa data register pa6 pa data register pa7 output function 0 0 1 pa ? =bz pa7= bz 0 0 0 pa ? = 0 pa7= 0 0 1 1 pa ? =bz pa7=in ? ut line 0 1 0 pa ? = 0 pa7=in ? ut line 1 0 d pa ? =in ? ut line pa7=d 1 1 pa ? =in ? ut line pa7=in ? ut line stands fo ? dont ca ? e d stands fo ? data 0 o ? 1 if the options have selected that only the p a6 pin is to function as a bz buzzer pin, then the p a7 pin can be used as a normal i/o pin. for the p a6 pin to function as a bz buzzer pin, p a6 must be setup as an output by setting bit p ac6 of the p ac port control register to zero. the p a6 data bit in the p a data register must also be set high to enable the buzzer output, if set low pin p a6 will remain low . in this way the p a6 bit can be used as an on/of f control for the bz buzze r pin p a6. if the p ac6 bit of the pac port control register is set high, then pin p a6 can still be used as an input even though the option has confgured it as a bz buzzer output. note that no matter what bpctl option is chosen for the buzzer , if the port control register has setup the pin to function as an input, then this will override the bpctl option selection and force the pin to always behave as an input pin. this arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the bpctl option chosen; the actual function of the pin can be changed dynamically by the application program by programming the appropriate port control register bit.

buzzer output pin control note: the above drawing shows the situation where both pins pa6 and pa7 are selected by bpctl option to be bz and bz buzzer pin outputs. the port control register of both pins must have already been setup as output. the data setup on pin pa7 has no effect on the buzzer outputs.
rev. 0.00 84 ?e?te??e? ??? ?01? rev. 0.00 85 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators confguration options confguration options refer to certa in options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device using the hardwa re programmi ng tools, once they are sel ected they cannot be changed la ter using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 o ? c ty ? e selection: erc o ? c ? ystal o ? hirc o ? ec (exte ? nal clock) 00: hxt (filte ? on) 01: erc (filte ? on) 10: hirc (filte ? off) 11: ec (filte ? off) ? hirc f ? equency selection: 4mhz ? 910khz ? ? mhz ? 8mhz 3 hxt ? ode selection: 455 k hz o ? 1m~ 1 ? mhz watchdog options 4 watchdog ti ? e ? function: always ena ? le by ? /w cont ? ol rc filter 5 rc flter for tmr & int0/int1 ? ena ? le o ? disa ? le lock options ? lock all 7 pa ? tial lock
rev. 0.00 8 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 87 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators application circuits pb ? pc 0/ o?c 1 pa 1/c1 out / tmr pc 1/ o?c ? pc ?/c? p v?? pc 5/c1 n vdd pc 4/ vcap pa ?/a1p/c? out pa 0/ cnp pa 3/a1n/ int 0 pa 7/a?e/ bz pa 4/a1e pa ?/a?n/ bz pa 5/a?p/ pfd i/o 5 i/o 1 i/o ? i/o3 i/o 4 dout i/o? i/o7 i/o8 v?? vcc rf ci?cuits
rev. 0.00 8? ?e?te??e? ??? ?01? rev. 0.00 87 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 0.00 88 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 89 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction set . as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they dif fer in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f poi nt as in the case of the call instruct ion. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. howeve r, whe n working wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 0.00 88 ?e?te??e? ??? ?01? rev. 0.00 89 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0 ~ 7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [ ? ] addm a ? [ ? ] add a ? x adc a ? [ ? ] adcm a ? [ ? ] ? ub a ? x ? ub a ? [ ? ] ? ubm a ? [ ? ] ? bc a ? [ ? ] ? bcm a ? [ ? ] daa [ ? ] add data me ? o ? y to acc add acc to data me ? o ? y add i ?? ediate data to acc add data me ? o ? y to acc with ca ?? y add acc to data ? e ? o ? y with ca ?? y ? u ? t ? act i ?? ediate data f ? o ? the acc ? u ? t ? act data me ? o ? y f ? o ? acc ? u ? t ? act data me ? o ? y f ? o ? acc with ? esult in data me ? o ? y ? u ? t ? act data me ? o ? y f ? o ? acc with ca ?? y ? u ? t ? act data me ? o ? y f ? o ? acc with ca ?? y ? ? esult in data me ? o ? y deci ? al adjust acc fo ? addition with ? esult in data me ? o ? y 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov z ? c ? ac ? ov c logic operation and a ? [ ? ] or a ? [ ? ] xor a ? [ ? ] andm a ? [ ? ] orm a ? [ ? ] xorm a ? [ ? ] and a ? x or a ? x xor a ? x cpl [ ? ] cpla [ ? ] logical and data me ? o ? y to acc logical or data me ? o ? y to acc logical xor data me ? o ? y to acc logical and acc to data me ? o ? y logical or acc to data me ? o ? y logical xor acc to data me ? o ? y logical and i ?? ediate data to acc logical or i ?? ediate data to acc logical xor i ?? ediate data to acc co ?? le ? ent data me ? o ? y co ?? le ? ent data me ? o ? y with ? esult in acc 1 1 1 1 note 1note 1note 1 1 1 1note 1 z z z z z z z z z z z increment & decrement inca [ ? ] inc [ ? ] deca [ ? ] dec [ ? ] inc ? e ? ent data me ? o ? y with ? esult in acc inc ? e ? ent data me ? o ? y dec ? e ? ent data me ? o ? y with ? esult in acc dec ? e ? ent data me ? o ? y 1 1 note 1 1note z z z z rotate rra [ ? ] rr [ ? ] rrca [ ? ] rrc [ ? ] rla [ ? ] rl [ ? ] rlca [ ? ] rlc [ ? ] rotate data me ? o ? y ? ight with ? esult in acc rotate data me ? o ? y ? ight rotate data me ? o ? y ? ight th ? ough ca ?? y with ? esult in acc rotate data me ? o ? y ? ight th ? ough ca ?? y rotate data me ? o ? y left with ? esult in acc rotate data me ? o ? y left rotate data me ? o ? y left th ? ough ca ?? y with ? esult in acc rotate data me ? o ? y left th ? ough ca ?? y 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a ? [ ? ] mov [ ? ] ? a mov a ? x move data me ? o ? y to acc move acc to data me ? o ? y move i ?? ediate data to acc 1 1 note 1 none none none bit operation clr [ ? ].i ? et [ ? ].i clea ? ? it of data me ? o ? y ? et ? it of data me ? o ? y 1 note 1 note none none
rev. 0.00 90 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 91 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators mnemonic description cycles flag affected branch jmp add ? ? z [ ? ] ? za [ ? ] ? z [ ? ].i ? nz [ ? ].i ? iz [ ? ] ? dz [ ? ] ? iza [ ? ] ? dza [ ? ] call add ? ret ret a ? x reti ju ?? unconditionally ? ki ? if data me ? o ? y is ze ? o ? ki ? if data me ? o ? y is ze ? o with data ? ove ? ent to acc ? ki ? if ? it i of data me ? o ? y is ze ? o ? ki ? if ? it i of data me ? o ? y is not ze ? o ? ki ? if inc ? e ? ent data me ? o ? y is ze ? o ? ki ? if dec ? e ? ent data me ? o ? y is ze ? o ? ki ? if inc ? e ? ent data me ? o ? y is ze ? o with ? esult in acc ? ki ? if dec ? e ? ent data me ? o ? y is ze ? o with ? esult in acc ? u ?? outine call retu ? n f ? o ? su ?? outine retu ? n f ? o ? su ?? outine and load i ?? ediate data to acc retu ? n f ? o ? inte ?? u ? t ? 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note ? ? ? ? none none none none none none none none none none none none none table read tabrd [ ? ] tabrdl [ ? ] read ta ? le to tblh and data me ? o ? y read ta ? le (last ? age) to tblh and data me ? o ? y ? note ? note none none miscellaneous nop clr [ ? ] ? et [ ? ] clr wdt ? wap [ ? ] ? wapa [ ? ] halt no o ? e ? ation clea ? data me ? o ? y ? et data me ? o ? y clea ? watchdog ti ? e ? ? wa ? ni ?? les of data me ? o ? y ? wa ? ni ?? les of data me ? o ? y with ? esult in acc ente ? ? owe ? down ? ode 1 1 note 1 note 1 1 note 1 1 none none none to ? pdf none none to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution.
rev. 0.00 90 ?e?te??e? ??? ?01? rev. 0.00 91 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 0.00 9 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 93 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 0.00 9? ?e?te??e? ??? ?01? rev. 0.00 93 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 0.00 94 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 95 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 0.00 94 ?e?te??e? ??? ?01? rev. 0.00 95 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i = 0 ~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i = 0 ~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i = 0 ~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i = 0 ~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); ( i = 0 ~6) [m].7 [ m].0 affected f ag(s) none
rev. 0.00 9 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 97 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i = 0 ~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); ( i = 0 ~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i = 0 ~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m] = 0 affected f ag(s) none
rev. 0.00 9? ?e?te??e? ??? ?01? rev. 0.00 97 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc = 0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m] = 0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc = 0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 0.00 98 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 99 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7 ~ [ m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3 ~ a cc.0 [ m].7 ~ [ m].4 acc.7 ~ a cc.4 [ m].3 ~ [ m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] = 0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m] = 0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i = 0 affected f ag(s) none
rev. 0.00 98 ?e?te??e? ??? ?01? rev. 0.00 99 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators tabrd [m] read ta ble to t blh a nd d ata m emory description the p rogram c ode a ddressed b y t he t able p ointer ( tbhp a nd t blp) is m oved t o t he sp ecifed data m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 0.00 100 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 101 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0. ?? 8 D 0. ? 44 b 0.150 D 0.157 c 0.01 ? D 0.0 ? 0 c 0.38 ? D 0.40 ? d D D 0.0 ? 9 e D 0.050 D f 0.004 D 0.010 g 0.01 ? D 0.050 h 0.007 D 0.010 0 D 8 symbol dimensions in mm min. nom. max. a 5.79 D ? . ? 0 b 3.81 D 3.99 c 0.30 D 0.51 c 9.80 D 10. ? 1 d D D 1.75 e D 1. ? 7 D f 0.10 D 0. ? 5 g 0.41 D 1. ? 7 h 0.18 D 0. ? 5 0 D 8
rev. 0.00 100 ?e?te??e? ??? ?01? rev. 0.00 101 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0. ?? 8 0. ? 44 b 0.150 0.158 c 0.008 0.01 ? c' 0.335 0.347 d 0.049 0.0 ? 5 e 0.0 ? 5 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 ? . ? 0 b 3.81 4.01 c 0. ? 0 0.30 c' 8.51 8.81 d 1. ? 4 1. ? 5 e 0. ? 4 f 0.10 0. ? 5 g 0.38 1. ? 7 h 0.18 0. ? 5 0 8
rev. 0.00 10 ? ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 103 ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators reel dimensions 16-pin nsop (150mil) ? y ?? ol description dimensions in mm a reel oute ? dia ? ete ? 330.01.0 b reel inne ? dia ? ete ? 100.01.5 c ?? indle hole dia ? ete ? 13.0 +0.5/-0. ? d key ? lit width ? .00.5 t1 ?? ace between flang 1 ? .8 +0.3/-0. ? t ? reel thickness ?? . ? 0. ? 20-pin ssop (150mil) ? y ?? ol description dimensions in mm a reel oute ? dia ? ete ? 330.01.0 b reel inne ? dia ? ete ? 100.01.5 c ?? indle hole dia ? ete ? 13.0 +0.5/-0. ? d key ? lit width ? .00.5 t1 ?? ace between flang 1 ? .8 +0.3/-0. ? t ? reel thickness ?? . ? 0. ?
rev. 0.00 10? ?e?te??e? ??? ?01? rev. 0.00 103 ? e ? te ?? e ? ??? ? 01 ? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators carrier tape dimensions

16-pin nsop (150mil) symbol description dimensions in mm w ca ?? ie ? ta ? e width 1 ? .00.3 p cavity pitch 8.00.1 e pe ? fo ? ation position 1.750.10 f cavity to pe ? fo ? ation(width di ? ection) 7.50.1 d pe ? fo ? ation dia ? ete ? 1.55 +0.10/-0.00 d1 cavity hole dia ? ete ? 1.50 +0. ? 5/-0.00 p0 pe ? fo ? ation pitch 4.00.1 p1 cavity to pe ? fo ? ation(length di ? ection) ? .00.1 a0 cavity length ? .50.1 b0 cavity width 10.30.1 k0 cavity de ? th ? .10.1 t ca ?? ie ? ta ? e thickness 0.300.05 c cove ? ta ? e width 13.30.1 20-pin ssop (150mil) symbol description dimensions in mm w ca ?? ie ? ta ? e width 1 ? .0 +0.3/-0.1 p cavity pitch 8.00.1 e pe ? fo ? ation position 1.750.10 f cavity to pe ? fo ? ation(width di ? ection) 7.500.10 d pe ? fo ? ation dia ? ete ? 1.50 +0.10/-0.00 d1 cavity hole dia ? ete ? 1.50 +0. ? 5/-0.00 p0 pe ? fo ? ation pitch 4.00.1 p1 cavity to pe ? fo ? ation(length di ? ection) ? .00.1 a0 cavity length ? .50.1 b0 cavity width 9.00.1 k0 cavity de ? th ? .30.1 t ca ?? ie ? ta ? e thickness 0.300.05 c cove ? ta ? e width 13.30.1
rev. 0.00 104 ? e ? te ?? e ? ??? ? 01 ? rev. 0.00 pb ?e?te??e? ??? ?01? HT45F12 8-bit flash mcu with op amps & comparators HT45F12 8-bit flash mcu with op amps & comparators holtek semiconductor inc. (headquarters) no.3 ? c ? eation rd. ii ? ? cience pa ? k ? hsinchu ? taiwan tel: 88 ? -3-5 ? 3-1999 fax: 88 ? -3-5 ? 3-1189 htt ? ://www.holtek.co ? .tw holtek semiconductor inc. (taipei sales offce) 4f- ?? no. 3- ?? yuanqu ? t. ? nankang ? oftwa ? e pa ? k ? tai ? ei 115 ? taiwan tel: 88 ? - ? - ?? 55-7070 fax: 88 ? - ? - ?? 55-7373 fax: 88 ? - ? - ?? 55-7383 (inte ? national sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit a ? p ? oductivity building ? no.5 gaoxin m ? nd road ? nanshan dist ? ict ? ? henzhen ? china 518057 tel: 8 ? -755-8 ? 1 ? -9908 ? 8 ? -755-8 ? 1 ? -9308 fax: 8 ? -755-8 ? 1 ? -97 ?? holtek semiconductor (usa), inc. (north america sales offce) 4 ? 7 ? 9 f ? e ? ont blvd. ? f ? e ? ont ? ca 94538 ? u ? a tel: 1-510- ? 5 ? -9880 fax: 1-510- ? 5 ? -9885 htt ? ://www.holtek.co ? co ? y ? ight ? ? 01 ? ? y holtek ? emiconductor inc. the info ?? ation a ?? ea ? ing in this data ? heet is ? elieved to ? e accu ? ate at the ti ? e of ? u ? lication. howeve ?? holt ek assu ? es no ? es ? onsi ? ility a ? ising f ? o ? the use of the s ? ecifications desc ? i ? ed. the a ?? lications ? entioned he ? ein a ? e used solely fo ? the ? u ?? ose of illust ? ation and holtek ? akes no wa ?? anty o ? ? e ?? esentation that such a ?? lications will ? e suita ? le without fu ? the ? ? odification ? no ? ? eco ?? ends the use of its ?? oducts fo ? a ?? lication that ? ay ?? esent a ? isk to hu ? an life due to ? alfunction o ? othe ? wise. holtek's ?? oducts a ? e not autho ? ized fo ? use as c ? itical co ?? onents in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the ? ost u ? -to-date info ?? ation ? ? lease visit ou ? we ? site at htt ? ://www.holtek.co ? .tw.

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